参数资料
型号: MAX1300AEUG+T
厂商: Maxim Integrated Products
文件页数: 19/31页
文件大小: 0K
描述: IC ADC 16BIT SRL 115KSPS 24TSSOP
产品培训模块: Obsolescence Mitigation Program
标准包装: 2,500
位数: 16
采样率(每秒): 115k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 976mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 带卷 (TR)
输入数目和类型: 8 个单端,单极;8 个单端,双极;4 个差分,双极
MAX1300/MAX1301
Bridge Application
The MAX1300/MAX1301 convert 1kHz signals more
accurately than a similar sigma-delta converter that
might be considered in bridge applications. The input
impedance of the MAX1300, in combination with the cur-
rent-limiting resistors, can affect the gain of the
MAX1300. In many applications this error is acceptable,
but for applications that cannot tolerate this error, the
MAX1300 inputs can be buffered (Figure 20). Connect
the bridge to a low-offset differential amplifier and then
the true-differential inputs of the MAX1300/MAX1301.
Larger excitation voltages take advantage of more of the
(±3 x VREF)/4 differential input voltage range. Select an
input voltage range that matches the amplifier output. Be
aware of the amplifier offset and offset-drift errors when
selecting an appropriate amplifier.
Dynamically Adjusting the Input Range
Software control of each channel’s analog input range
and the unipolar endpoint overlap specification make it
possible for the user to change the input range for a
channel dynamically and improve performance in some
applications. Changing the input range results in a
small LSB step-size over a wider output voltage range.
For example, by switching between a (-3 x VREF)/2 to
0V range and a 0 to (+3 x VREF)/2 range, an LSB is
but the input voltage range effectively spans from
(-3 x VREF)/2 to (+3 x VREF)/2 (FSR = 3 x VREF).
Layout, Grounding, and Bypassing
Careful PC board layout is essential for best system per-
formance. Boards should have separate analog and
digital ground planes and ensure that digital and analog
signals are separated from each other. Do not run ana-
log and digital (especially clock) lines parallel to one
another, or digital lines underneath the device package.
Figure 1 shows the recommended system ground con-
nections. Establish an analog ground point at AGND1
and a digital ground point at DGND. Connect all analog
grounds to the star analog ground. Connect the digital
grounds to the star digital ground. Connect the digital
ground plane to the analog ground plane at one point.
For lowest noise operation, make the ground return to
the star ground’s power-supply low impedance and as
short as possible.
High-frequency noise in the AVDD1 power supply
degrades the ADC’s high-speed comparator perfor-
mance. Bypass AVDD1 to AGND1 with a 0.1F ceramic
surface-mount capacitor. Make bypass capacitor con-
nections as short as possible.
Parameter Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. This straight line is either a
best straight-line fit or a line drawn between the end-
points of the transfer function once offset and gain
errors have been nullified. The MAX1300/MAX1301 INL
is measured using the endpoint method.
() ×
×
32
65 536
4 096
VV
REF
,.
8- and 4-Channel, ±3 x VREF Multirange Inputs,
Serial 16-Bit ADCs
26
______________________________________________________________________________________
REF
REFCAP
AGND1
4.096V
BANDGAP
REFERENCE
5k
1x
SAR
ADC REF
4.096V
1.0
F
VRCTH
MAX1300
MAX1301
AVDD1
MAX6341
V+
1.0
F
OUT
GND
IN
Figure 18. External Reference Operation
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