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参数资料
型号： MAX1302BEUG+T
厂商： Maxim Integrated Products
文件页数： 15/31页
文件大小： 0K
描述： IC ADC 16BIT SRL 115KSPS 24TSSOP
标准包装： 2,500
位数： 16
采样率（每秒）： 115k
数据接口： MICROWIRE?，QSPI?，串行，SPI?
转换器数目： 1
功率耗散（最大）： 1.11W
电压电源： 模拟和数字
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 24-TSSOP（0.173"，4.40mm 宽）
供应商设备封装： 24-TSSOP
包装： 带卷 (TR)
输入数目和类型： 8 个单端，单极；8 个单端，双极；4 个差分，单极；4 个差分，双极
MAX1302
Mode Control
The MAX1302 contains one byte-wide mode-control
register. The timing diagram of Figure 15 shows how to
use the mode-control byte, and the mode-control byte
format is shown in Table 7. The mode-control byte is
used to select the conversion method and to control the
power modes of the MAX1302.
Selecting the Conversion Method
The conversion method is selected using the mode-con-
trol byte (see the
Mode Control section), and the conver-
sion is initiated using a conversion start command (Table
3, and Figures 2, 3, and 4). The MAX1302 converts ana-
log signals to digital data using one of three methods:
External Clock Mode, Mode 0 (Figure 2)
Highest maximum throughput (see the
Electrical
Characteristics table)
User controls the sample instant
CS remains low during the conversion
User supplies SCLK throughout the ADC con-
version and reads data at DOUT
External Acquisition Mode, Mode 1 (Figure 3)
Lowest maximum throughput (see the
Electrical
Characteristics table)
User controls the sample instant
User supplies two bytes of SCLK, then drives
CS high to relieve processor load while the
ADC converts
After SSTRB transitions high, the user supplies
two bytes of SCLK and reads data at DOUT
Internal Clock Mode, Mode 2 (Figure 4)
High maximum throughput (see the
Electrical
Characteristics table)
The internal clock controls the sampling instant
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
22
______________________________________________________________________________________
1 LSB =
FSR x VREF
65,536 x 4.096V
BINARY
OUTPUT
CODE
(LSB
[hex])
FFFF
FFFE
FFFD
8001
8000
7FFF
0003
0002
0001
0000
FSR
0
1
2
3
32,768
65,533 65,535
INPUT VOLTAGE (LSB [DECIMAL])
(AGND1)
FSR
Figure 13. Ideal Unipolar Transfer Function, Single-Ended
Input, -FSR to 0
1 LSB =
FSR x VREF
65,536 x 4.096V
BINARY
OUTPUT
CODE
(LSB
[hex])
FFFF
FFFE
FFFD
8001
8000
7FFF
0003
0002
0001
0000
FSR
0
1
2
3
32,768
65,533 65,535
INPUT VOLTAGE (LSB [DECIMAL])
(AGND1)
FSR
Figure 14. Ideal Unipolar Transfer Function, Single-Ended
Input, 0 to +FSR
1 LSB =
FSR x VREF
65,536 x 4.096V
BINARY
OUTPUT
CODE
(LSB
[hex])
FFFF
FFFE
FFFD
8001
8000
7FFF
0003
0002
0001
0000
FSR
-32,768 -32,766
0
+32,765 +32,767
INPUT VOLTAGE (LSB [DECIMAL])
AGND1 (DIF/SGL = 0)
0V (DIF/SGL = 1)
FSR
-1
+1
Figure 12. Ideal Bipolar Transfer Function, Single-Ended or
Differential Input
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