MAX1302
Power Supplies
To maintain a low-noise environment, the MAX1302
provides separate power supplies for each section of
circuitry. Table 1 shows the four separate power sup-
plies. Achieve optimal performance using separate
AVDD1, AVDD2, DVDD, and DVDDO supplies.
Alternatively, connect AVDD1, AVDD2, and DVDD
together as close to the device as possible for a conve-
nient power connection. Connect AGND1, AGND2,
AGND3, DGND, and DGNDO together as close as pos-
sible to the device. Bypass each supply to the corre-
sponding ground using a 0.1F capacitor (Table 1). If
significant low-frequency noise is present, add a 10F
capacitor in parallel with the 0.1F bypass capacitor.
Converter Operation
The MAX1302 ADC features a fully differential, succes-
sive-approximation register (SAR) conversion tech-
nique and an on-chip T/H block to convert voltage
signals into a 16-bit digital result. Both single-ended
and differential configurations are supported with pro-
grammable unipolar and bipolar signal ranges.
Track-and-Hold Circuitry
The MAX1302 features a switched-capacitor T/H archi-
tecture that allows the analog input signal to be stored as
charge on sampling capacitors. See Figures 2, 3, and 4
for T/H timing and the sampling instants for each operat-
ing mode. The MAX1302 analog input circuitry buffers
the input signal from the sampling capacitors, resulting
in a constant analog input impedance with varying input
voltage (Figure 5).
Analog Input Circuitry
Select differential or single-ended conversions using the
associated analog input configuration byte (Table 2).
The analog input signal source must be capable of dri-
ving the ADC’s 6k
input resistance (Figure 6).
Figure 6 shows the simplified analog input circuit. The
analog inputs are ±6V fault tolerant and are protected
by back-to-back diodes. The summing junction voltage,
VSJ, is a function of the channel’s input common-mode
voltage:
V
R
RR
V
R
RR
V
SJ
CM
.
=
+
×+
+
×
1
12
2 375
1
12
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
14
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Table 1. MAX1302 Power Supplies and Bypassing
POWER
SUPPLY/GROUND
SUPPLY VOLTAGE
RANGE (V)
TYPICAL SUPPLY
CURRENT (mA)
CIRCUIT SECTION
BYPASSING
DVDDO/DGNDO
2.7 to 5.25
0.2
Digital I/O
0.1F to DGNDO
AVDD2/AGND2
4.75 to 5.25
17.5
Analog Circuitry
0.1F to AGND2
AVDD1/AGND1
4.75 to 5.25
3.0
Analog Circuitry
0.1F to AGND1
DVDD/DGND
4.75 to 5.25
0.9
Digital Control Logic and
Memory
0.1F to DGND
Table 2. Analog Input Configuration Byte
BIT
NUMBER
NAME
DESCRIPTION
7
START
Start Bit. The first logic 1 after
CS goes low defines the beginning of the analog input configuration byte.
6C2
5C1
4C0
Channel-Select Bits. SEL[2:0] select the analog input channel to be configured (Tables 4 and 5).
3
DIF/
SGL
Differential or Single-Ended Configuration Bit. DIF/
SGL = 0 configures the selected analog input channel
for single-ended operation. DIF/
SGL = 1 configures the channel for differential operation. In single-ended
mode, input voltages are measured between the selected input channel and AGND1, as shown in
Table 4. In differential mode, the input voltages are measured between two input channels, as shown in
Table 5. Be aware that changing DIF/
SGL adjusts the FSR, as shown in Table 6.
2R2
1R1
0R0
Input-Range-Select Bits. R[2:0] select the input voltage range, as shown in Table 6 and Figure 7.