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参数资料
| 型号： | MAX1303BEUP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT MULT RANGE 20TSSOP |
| 标准包装： | 2,500 |
| 位数： | 16 |
| 采样率（每秒）： | 115k |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 105.5mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个单端，单极；4 个单端，双极；2 个差分，双极 |
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MAX1303
4-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
______________________________________________________________________________________
19
Differential Common-Mode Range
The MAX1303 differential common-mode range
(VCMDR) must remain within -4.75V to +5.5V to obtain
valid conversion results. The differential common-mode
range is defined as:
In addition to the common-mode input voltage limita-
tions, each individual analog input must be limited to
±6V with respect to AGND1.
The range-select bits R[2:0] in the analog input config-
uration bytes determine the full-scale range for the cor-
responding channel (Tables 2 and 6). Figures 8, 9, and
10 show the valid analog input voltage ranges for the
MAX1303 when operating with FSR = VREF/2, FSR =
VREF, and FSR = 2 x VREF, respectively. The shaded
area contains the valid common-mode voltage ranges
that support the entire FSR.
Digital Interface
The MAX1303 features a serial interface that is compat-
ible with SPI/QSPI and MICROWIRE devices. DIN,
DOUT, SCLK, CS, and SSTRB facilitate bidirectional
communication between the MAX1303 and the master
at SCLK rates up to 10MHz (internal clock mode, mode
2), 3.67MHz (external clock mode, mode 0), or
4.39MHz (external acquisition mode, mode 1). The
master, typically a microcontroller, should use the
CPOL = 0, CPHA = 0, SPI transfer format, as shown in
the timing diagrams of Figures 1, 2, and 3.
The digital interface is used to:
Select single-ended or true-differential input channel
configurations
Select the unipolar or bipolar input range
Select the mode of operation:
External clock (mode 0)
External acquisition (mode 1)
Internal clock (mode 2)
Reset (mode 4)
Partial power-down (mode 6)
Full power-down (mode 7)
Initiate conversions and read results
Chip Select (
CS)
CS enables communication with the MAX1303. When CS is
low, data is clocked into the device from DIN on the rising edge
of SCLK and data is clocked out of DOUT on the falling edge
of SCLK. When CS is high, activity on SCLK and DIN is ignored
and DOUT is high impedance allowing DOUT to be shared
with other peripherals. SSTRB is never high impedance
and therefore cannot be shared with other peripherals.
V
CH
CMDR
_
=
+
() + ()
2
INPUT VOLTAGE (V)
COMMON-MODE
VOLTAGE
(V)
6
4
2
0
-2
-4
-6
-4
-2
0
2
4
6
-6
-8
8
VREF = 4.096V
Figure 8. Common-Mode Voltage vs. Input Voltage (FSR = VREF)
INPUT VOLTAGE (V)
COMMON-MODE
VOLTAGE
(V)
6
4
2
0
-2
-4
-6
-4
-2
0
2
4
6
-6
-8
8
VREF = 4.096V
Figure 9. Common-Mode Voltage vs. Input Voltage (FSR = 2 x
VREF)
INPUT VOLTAGE (V)
COMMON-MODE
VOLTAGE
(V)
6
4
2
0
-2
-4
-6
-4
-2
0
2
4
6
-6
-8
8
VREF = 4.096V
Figure 10. Common-Mode Voltage vs. Input Voltage (FSR = 4 x
VREF)
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