参数资料
型号: MAX1346BETX+
厂商: Maxim Integrated Products
文件页数: 13/39页
文件大小: 0K
描述: IC ADC/DAC 12BIT W/FIFO 36WQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
类型: ADC,DAC
分辨率(位): 12 b
采样率(每秒): 225k
数据接口: MICROWIRE?,QSPI?,串行,SPI?
电压电源: 模拟和数字
电源电压: 4.75 V ~ 5.25 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-WFQFN 裸露焊盘
供应商设备封装: 36-TQFN 裸露焊盘(6x6)
包装: 管件
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
20
______________________________________________________________________________________
A conversion is not performed if it is requested on a
channel or one of the channel pairs that has been con-
figured as
CNVST or REF2. For channels configured as
differential pairs, the CHSEL0 bit is ignored and the two
pins are treated as a single differential channel. For the
MAX1346/MAX1348, the CHSEL2 bit must be zero.
Channels 4–7 are invalid. Any scans or averages on
these channels can cause corrupt data.
Select scan mode 00 or 01 to return one result per sin-
gle-ended channel and one result per differential pair
within the selected scanning range (set by bits 2 and 1,
SCAN1 and SCAN0), plus one temperature result if
selected. Select scan mode 10 to scan a single input
channel numerous times, depending on NSCAN1 and
NSCAN0 in the ADC averaging register (Table 9).
Select scan mode 11 to return only one result from a
single channel.
Setup Register
Issue a command byte to the setup register to config-
ure the clock, reference, power-down modes, and ADC
single-ended/differential modes. Table 5 details the bits
in the setup-register command byte. Bits 5 and 4
(CKSEL1 and CKSEL0) control the clock mode, acqui-
sition and sampling, and the conversion start. Bits 3
and 2 (REFSEL1 and REFSEL0) set the device for either
internal or external reference. Bits 1 and 0 (DIFFSEL1
and DIFFSEL0) address the ADC unipolar-mode and
bipolar-mode registers and configure the analog-input
channels for differential operation.
The ADC reference is always on if any of the following
conditions are true:
1) The FBGON bit is set to one in the reset register.
2) At least one DAC output is powered up and
REFSEL[1:0] (in the setup register) = 00.
3) At least one DAC is powered down through the
100k to VREF and REFSEL[1:0] = 00.
If any of the above conditions exist, the ADC reference is
always on, but there is a 188 clock-cycle delay before
temperature-sensor measurements begin, if requested.
Table 4. Conversion Register*
BIT
NAME
BIT
FUNCTION
7 (MSB)
Set to one to select conversion register.
X
6
Don’t care.
CHSEL2
5
Analog-input channel select
(MAX1340/MAX1342). Set to 0 on
MAX1346/MAX1348.
CHSEL1
4
Analog-input channel select.
CHSEL0
3
Analog-input channel select.
SCAN1
2
Scan-mode select.
SCAN0
1
Scan-mode select.
TEMP
0 (LSB)
Set to one to take a single temp-
erature measurement. The first
conversion result of a scan contains
temperature information.
CHSEL2**
CHSEL1
CHSEL0
SELECTED
CHANNEL
(N)
0
AIN0
0
1
AIN1
0
1
0
AIN2
0
1
AIN3
1
0
AIN4
1
0
1
AIN5
1
0
AIN6
1
AIN7
SCAN1
SCAN0
SCAN MODE
(CHANNEL N IS SELECTED BY
BITS CHSEL2, CHSEL1, AND CHSEL0)
0
Scans channels 0 through N.
01
Scans channels N through the highest
numbered channel.
10
Scans channel N repeatedly. The ADC
averaging register sets the number of
results.
11
No scan. Converts channel N once only.
*
See below for bit details.
**
Channels 4–7 are invalid on the MAX1346/MAX1348. Set
CHSEL2 bit to 0 on those devices.
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