参数资料
| 型号： | MAX1358BETL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 4/71页 |
| 文件大小： | 0K |
| 描述： | IC DAS 16BIT 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 数据采集系统（DAS） |
| 分辨率（位）： | 16 b |
| 采样率（每秒）： | 21.94k |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 电压电源： | 模拟和数字 |
| 电源电压： | 1.8 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
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MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
12
______________________________________________________________________________________
TIMING CHARACTERISTICS (Figures 1 and 19)
(AVDD = DVDD = +1.8V to +3.6V, external VREF = +1.25V, fCLK32K = 32.768kHz (external clock), CREG = 10F, CCPOUT = 10F,
10F between CF+ and CF-, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25
°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Operating Frequency
fSCLK
010
MHz
SCLK Cycle Time
tCYC
100
ns
SCLK Pulse-Width High
tCH
40
ns
SCLK Pulse-Width Low
tCL
40
ns
DIN to SCLK Setup
tDS
30
ns
DIN to SCLK Hold
tDH
0ns
SCLK Fall to DOUT Valid
tDO
CL = 50pF, Figure 2
40
ns
CS Fall to DOUT Enable
tDV
CL = 50pF, Figure 2
48
ns
CS Rise to DOUT Disable
tTR
CL = 50pF, Figure 2
48
ns
CS to SCLK Rise Setup
tCSS
20
ns
CS to SCLK Rise Hold
tCSH
0ns
DVDD Monitor Timeout Period
tDSLP
(Note 16)
1.5
s
Wake-Up (WU) Pulse Width
tWU
Minimum pulse width required to detect a
wake-up event
1s
Shutdown Delay
tDPU
The delay for
SHDN to go high after a valid
wake-up event
1s
The turn-on time for the high-frequency
clock and FLL (FLLE = 1) (Note 17)
10
ms
HFCLK Turn-On Time (Note 2)
tDFON
If FLLE = 0, the turn-on time for the high-
frequency clock (Notes 7, 18)
10
s
CRDY to
INT Delay
tDFI
The delay for CRDY to go low after the
HFCLK clock output has been enabled
(Note 19)
7.82
ms
HFCLK Disable Delay
tDFOF
The delay after a shutdown command has
asserted and before HFCLK is disabled
(Note 20)
1.95
ms
SHDN Assertion Delay
tDPD
(Note 21)
2.93
ms
Note 16: The delay for the sleep voltage monitor output,
RESET, to go high after VDD rises above the reset threshold. This is largely
driven by the startup of the 32kHz oscillator.
Note 17: FLLE is gated by an AND function with three inputs—the external
RESET signal, the internal DVDD monitor output, and the
external
SHDN signal. The time delay is timed from the internal LOVDD going high or the external RESET going high,
whichever happens later. HFCLK always starts in the low state.
Note 18: If FLLE = 0, the internal signal CRDY is not generated by the FLL block and
INT or INT is deasserted.
Note 19: CRDY is used as an interrupt signal to inform the C that the high-frequency clock has started. Only valid if FLLE = 1.
Note 20: tDFOF gives the C time to clean up and go into sleep-override mode properly.
Note 21: tDPD is greater than the HFCLK delay to clean up before losing power.
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