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参数资料
| 型号： | MAX1396MUB+T |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | ADC |
| 英文描述： | 1.5V to 3.6V, 312.5ksps, 1-Channel True-Differential/2-Channel Single-Ended, 12-Bit, SAR ADCs |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10 |
| 封装： | MO-187C-BA, MICRO SOP-10 |
| 文件页数： | 14/19页 |
| 文件大小： | 1037K |
| 代理商： | MAX1396MUB+T |
MAX1393/MAX1396
4
_______________________________________________________________________________________
1.5V to 3.6V, 312.5ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 12-Bit, SAR ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1F, fSCLK = 5MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Tri-State Leakage Current
ILT
OE = VDD
±1
A
Tri-State Output Capacitance
COUT
OE = VDD
10
pF
POWER SUPPLY
Positive Supply Voltage
VDD
1.5
3.6
V
VDD = 1.6V
176
200
fSAMPLE = 100ksps
VDD = 3V
225
260
VDD = 1.6V
520
600
fSAMPLE = 312.5ksps
VDD = 3V
710
800
Power-down mode (Note 4)
5
10
Positive Supply Current (Note 3)
IDD
Power-down mode (Note 5)
0.2
±2.5
A
Power-Supply Rejection
PSR
VDD = 1.5V to 3.6V, full-scale input (Note 6)
±150
±1000
V/V
TIMING CHARACTERISTICS
(VDD = +1.5V to +3.6V, VREF = VDD, CREF = 0.1F, fSCLK = 5MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.) (Figure 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Clock Period
tCP
200
10,000
ns
SCLK Pulse-Width High
tCH
90
ns
SCLK Pulse-Width Low
tCL
90
ns
CS Fall to SCLK Rise Setup
tCSS
80
ns
SCLK Rise to CS Fall Ignore
tCSO
0ns
SCLK Fall to DOUT Valid
tDOV
CLOAD = 0 to 30pF
10
80
ns
OE Rise to DOUT Disable
tDOD
620
ns
OE Fall to DOUT Enable
tDOE
920
ns
CS Pulse-Width High or Low
tCSW
80
ns
OE Pulse-Width High or Low
tOEW
80
ns
CH1/CH2 Setup Time (to the
First SCLK)
tCHS
MAX1396 only
10
ns
CH1/CH2 Hold Time (to the First
SCLK)
tCHH
MAX1396 only
0
ns
UNI/BIP Setup Time (to the First
SCLK)
tUBS
MAX1393 only
10
ns
UNI/BIP Hold Time (to the First
SCLK)
tUBH
MAX1393 only
0
ns
Note 1: VDD = 1.5V, VREF = 1.5V, and VAIN = 1.5V.
Note 2: VDD = 1.5V, VREF = 1.5V, VAIN = 1.5VP-P, fSCLK = 5MHz, fSAMPLE = 312.5ksps, and fIN (sine wave) = 75kHz.
Note 3: All digital inputs swing between VDD and GND. VREF = VDD,fIN = 75kHz sine wave, VAIN = VREFP-P, CLOAD = 30pF on DOUT.
Note 4: CS = VDD, OE = UNI/BIP = CH1/CH2 = VDD or GND, SCLK is active.
Note 5: CS = VDD, OE = UNI/BIP = CH1/CH2 = VDD or GND, SCLK is inactive.
Note 6: Change in VAIN at code boundary 4094.5.
相关PDF资料 |
PDF描述 |
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