参数资料
型号: MAX1396MUB+T
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: ADC
英文描述: 1.5V to 3.6V, 312.5ksps, 1-Channel True-Differential/2-Channel Single-Ended, 12-Bit, SAR ADCs
中文描述: 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO10
封装: MO-187C-BA, MICRO SOP-10
文件页数: 3/19页
文件大小: 1037K
代理商: MAX1396MUB+T
AutoShutdown Mode
The ADC automatically powers down on the SCLK
falling edge that clocks out the LSB. This is the falling
edge after the 15th SCLK. DOUT goes low when the
LSB has been clocked into the master (C) on the 16th
rising SCLK edge.
Alternatively, drive OE high to force the MAX1393/
MAX1396 into power-down. Whenever OE goes high,
the ADC powers down and disables DOUT regardless
of CS, SCLK, or the state of the ADC. DOUT enters a
high-impedance state after tDOD.
External Reference
The MAX1393/MAX1396 use an external reference
between 0.6V and (VDD + 50mV). Bypass REF with a
0.1F capacitor to GND for best performance (see the
Typical Operating Circuit).
Serial Interface
The MAX1393/MAX1396 serial interface is fully compati-
ble with SPI, QSPI, and MICROWIRE (see Figure 7). If a
serial interface is available, set the C’s serial interface
in master mode so the C generates the serial clock.
Choose a clock frequency between 100kHz and 5MHz.
CS and OE can be connected together and driven
simultaneously. OE can also be connected to GND if the
DOUT bus is not shared and driven independently.
SPI and MICROWIRE
When using SPI or MICROWIRE, make the C the bus
master and set CPOL = 0 and CPHA = 0 or CPOL = 1
and CPHA = 1. (These are the bits in the SPI or
MICROWIRE control register.) Two consecutive 1-byte
reads are required to get the entire 12-bit result from
the ADC. DOUT transitions on SCLK’s falling edge and
is clocked into the C on the SCLK’s rising edge. See
Figure 7 for connections and Figures 8 and 9 for timing
diagrams. The conversion result contains 4 zeros, fol-
lowed by the 12 data bits with the data in MSB-first for-
mat. When using CPOL = 0 and CPHA = 0 or CPOL = 1
and CPHA = 1, the MSB of the data is clocked into the
C on the SCLK’s fifth rising edge. To be compatible
with SPI and MICROWIRE, connect CS and OE togeth-
er and drive simultaneously.
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. However, the MAX1393/MAX1396 require 16
clock cycles from the C to clock out the 12 bits of
data. See Figure 7 for connections and Figures 8 and 9
for timing diagrams. The conversion result contains 4
zeros, followed by the 12 data bits with the data in
MSB-first format. When using CPOL = 0 and CPHA = 0
or CPOL = 1 and CPHA = 1, the MSB of the data is
clocked into the C on the SCLK’s fifth rising edge. To
be compatible with QSPI, connect CS and OE together
and drive simultaneously.
DSP Interface
Figure 10 shows the timing for DSP operation. Figure
11 shows the connections between the MAX1393/
MAX1396 and several common DSPs.
MAX1393/MAX1396
______________________________________________________________________________________
11
1.5V to 3.6V, 312.5ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 12-Bit, SAR ADCs
MAX1393
MAX1396
OE
a) SPI
I/O
SCK
CS
DOUT
MISO
I/O
UNI/BIP
(CH1/CH2)*
SCLK
MAX1393
MAX1396
OE
CS
SCK
CS
DOUT
MISO
I/O
UNI/BIP
(CH1/CH2)*
SCLK
MAX1393
MAX1396
OE
I/O
SK
CS
DOUT
SI
I/O
UNI/BIP
(CH1/CH2)*
SCLK
b) QSPI
c) MICROWIRE
*INDICATES THE MAX1396
Figure 7. Common Serial-Interface Connections to the
MAX1393/MAX1396
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