参数资料
| 型号： | MAX1403CAI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/36页 |
| 文件大小： | 0K |
| 描述： | IC ADC 18BIT LP 28-SSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,000 |
| 位数： | 18 |
| 采样率（每秒）： | 480 |
| 数据接口： | QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 21.45mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 3 个差分，单极；3 个差分，双极；5 个伪差分，单极；5 个伪差分，双极 |
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MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
______________________________________________________________________________________
11
Pin Description
15
AIN5
Analog Input Channel 5. Used as a differential or pseudo-differential input with AIN6 (see On-Chip
Registers section).
NAME
FUNCTION
1
CLKIN
Clock Input. A crystal can be connected across CLKIN and CLKOUT. Alternatively, drive CLKIN with a
CMOS-compatible clock at a nominal frequency of 2.4576MHz or 1.024MHz, and leave CLKOUT uncon-
nected. Frequencies of 4.9152MHz and 2.048MHz may be used if the X2CLK control bit is set to 1.
PIN
2
CLKOUT
Clock Output. When deriving the master clock from a crystal, connect the crystal between CLKIN and
CLKOUT. In this mode, the on-chip clock signal is not available at CLKOUT. Leave CLKOUT unconnected
when CLKIN is driven with an external clock.
3
CS
Chip-Select Input. This active-low logic input is used to enable the digital interface. With CS hard-wired
low, the MAX1403 operates in its 3-wire interface mode with SCLK, DIN, and DOUT used to interface to
the device. CS is used either to select the device in systems with more than one device on the serial bus,
or as a frame-synchronization signal for the MAX1403, when a continuous SCLK is used.
4
RESET
Active-Low Reset Input. Drive low to reset the control logic, interface logic, digital filter, and analog modu-
lator to power-on status. RESET must be high and CLKIN must be toggling in order to exit reset.
5
DS1
Digital Input for Auxiliary Data Input Bit 1. The status of this bit is reflected in the output data by bit D4.
Used to communicate the status of DS1 via the serial interface.
6
DS0
Digital Input for Auxiliary Data Input Bit 0. The status of this bit is reflected in the output data by bit D3.
Used to communicate the status of DS0 via the serial interface.
7
OUT2
Transducer Excitation Current Source 2
8
OUT1
Transducer Excitation Current Source 1
9
AGND
Analog Ground. Reference point for the analog circuitry. AGND connects to the IC substrate.
10
V+
Analog Positive Supply Voltage (+2.7V to +3.6V).
11
AIN1
Analog Input Channel 1. May be used as a pseudo-differential input with AIN6 as common, or as the posi-
tive input of the AIN1/AIN2 differential analog input pair (see On-Chip Registers section).
12
AIN2
Analog Input Channel 2. May be used as a pseudo-differential input with AIN6 as common, or as the neg-
ative input of the AIN1/AIN2 differential analog input pair (see On-Chip Registers section).
13
AIN3
Analog Input Channel 3. May be used as a pseudo-differential input with AIN6 as common, or as the posi-
tive input of the AIN3/AIN4 differential analog input pair (see On-Chip Registers section).
14
AIN4
Analog Input Channel 4. May be used as a pseudo-differential input with AIN6 as common, or as the neg-
ative input of the AIN3/AIN4 differential analog input pair (see On-Chip Registers section).
16
AIN6
Analog Input 6. May be used as a common point for AIN1 through AIN5 in pseudo-differential mode, or as
the negative input of the AIN5/AIN6 differential analog input pair (see On-Chip Registers section).
17
CALGAIN-
Negative Gain Calibration Input. Used for system gain calibration. It forms the negative input of a fully
differential input pair with CALGAIN+. Normally these inputs are connected to reference voltages in the
system. When system gain calibration is not required and the auto-sequence mode is used, the
CALGAIN+/CALGAIN- input pair provides an additional fully differential input channel.
18
CALGAIN+
Positive Gain Calibration Input. Used for system gain calibration. It forms the positive input of a fully
differential input pair with CALGAIN-. Normally these inputs are connected to reference voltages in the
system. When system gain calibration is not required and the auto-sequence mode is used, the
CALGAIN+/CALGAIN- input pair provides an additional fully differential input channel.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX1403EAI | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1403EAI+ | 功能描述:模数转换器 - ADC 18-Bit 5Ch 4.8ksps 1.25V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1403EAI+T | 功能描述:模数转换器 - ADC 18-Bit 5Ch 4.8ksps 1.25V Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1403EAI-T | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MAX1403EVKIT | 功能描述:数据转换 IC 开发工具 MAX1403 Eval Kit RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
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