参数资料
型号: MAX1422CCM+TD
厂商: Maxim Integrated Products
文件页数: 10/15页
文件大小: 0K
描述: IC ADC 12BIT 20MSPS 48LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
位数: 12
采样率(每秒): 20M
数据接口: 并联
转换器数目: 1
功率耗散(最大): 152mW
电压电源: 模拟和数字
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 带卷 (TR)
输入数目和类型: 1 个差分,双极
MAX1422
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
4
_______________________________________________________________________________________
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLK, CLK
±330
PD
-20
20
Input Current
OE
-20
20
A
Input Capacitance
10
pF
DIGITAL OUTPUTS (D0–D11)
Output Logic High
VOH
IOH = 200A
VDVDD
- 0.5
VDVDD
V
Output Logic Low
VOL
IOL = -200A
0
0.5
V
Three-State Leakage
-10
10
A
Three-State Capacitance
2pF
POWER REQUIREMENTS
Analog Supply Voltage
VAVDD
3.138
3.3
3.465
V
Digital Supply Voltage
VDVDD
2.7
3.3
3.63
V
Analog Supply Current
IAVDD
39
46
mA
Analog Supply Current with
Internal Reference in Shutdown
VREFIN = 0
37
44
mA
Analog Shutdown Current
PD = DVDD
20
A
Digital Supply Current
IDVDD
3mA
Digital Shutdown Current
PD = DVDD
20
A
Power Dissipation
PDISS
Analog power dissipation
137
152
mW
Power-Supply Rejection Ratio
PSRR
(Note 9)
±1
mV/V
TIMING CHARACTERISTICS
Maximum Clock Frequency
fCLK
Figure 6
20
MHz
Clock High
tCH
Figure 6, clock period 50ns
25
ns
Clock Low
tCL
Figure 6, clock period 50ns
25
ns
Pipeline Delay (Latency)
Figure 6
7
Clock
cycles
Aperture Delay
tAD
Figure 10
2
ns
Aperture Jitter
tAJ
Figure 10
2
ps
Data Output Delay
tOD
Figure 6
5
10
14
ns
Bus Enable Time
tBE
Figure 5
5
ns
Bus Disable Time
tBD
Figure 5
5
ns
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dBFS, internal reference, fCLK = 20MHz (50%
duty cycle); digital output load CL = 10pF,
≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Typical values are at TA = +25°C.)
Note 1: Internal reference, REFIN bypassed to AGND with a combination of 0.22F in parallel with 1nF capacitor.
Note 2: External 2.048V reference applied to REFIN.
Note 3: Internal reference disabled. VREFIN = 0, VREFP = 2.162V, VCML = 1.65V, and VREFN = 1.138V.
Note 4: IMD is measured with respect to either of the fundamental tones.
Note 5: Specifies the common-mode range of the differential input signal supplied to the MAX1422.
Note 6: VDIFF = VREFP - VREFN.
Note 7: Input bandwidth is measured at a 3dB level.
Note 8: VREFIN is internally biased to 2.048V through a 10k resistor.
Note 9: Measured as the ratio of the change in mid-scale offset voltage for a ±5% change in VAVDD, using the internal reference.
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