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参数资料
| 型号： | MAX1434ECQ+TD |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 2/22页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 50MSPS 100-TQFP |
| 标准包装： | 500 |
| 位数： | 10 |
| 采样率（每秒）： | 50M |
| 数据接口： | LVDS，串行 |
| 转换器数目： | 8 |
| 功率耗散（最大）： | 882mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | 100-TQFP 裸露焊盘 |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 8 个差分 |
MAX1434
Octal, 10-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
10
______________________________________________________________________________________
PIN
NAME
FUNCTION
1, 4, 7, 10, 16, 19, 22,
25, 26, 27, 30, 36, 89,
92, 96, 99, 100
GND
Ground. Connect all GND pins to the same potential.
2
IN1P
Channel 1 Positive Analog Input
3
IN1N
Channel 1 Negative Analog Input
5
IN2P
Channel 2 Positive Analog Input
6
IN2N
Channel 2 Negative Analog Input
8
IN3P
Channel 3 Positive Analog Input
9
IN3N
Channel 3 Negative Analog Input
11, 12, 13, 15, 37–42,
86, 87, 88
AVDD
Analog Power Input. Connect AVDD to a +1.7V to +1.9V power supply. Bypass AVDD to GND
with a 0.1F capacitor as close as possible to the device. Bypass the AVDD power plane to
the GND plane with a bulk
≥ 2.2F capacitor. Connect all AVDD pins to the same potential.
14, 31, 50, 51, 70,
75, 76
N.C.
No Connection. Not internally connected.
17
IN4P
Channel 4 Positive Analog Input
18
IN4N
Channel 4 Negative Analog Input
20
IN5P
Channel 5 Positive Analog Input
21
IN5N
Channel 5 Negative Analog Input
23
IN6P
Channel 6 Positive Analog Input
24
IN6N
Channel 6 Negative Analog Input
28
IN7P
Channel 7 Positive Analog Input
29
IN7N
Channel 7 Negative Analog Input
32
DT
Double-Termination Select. Drive DT high to select the internal 100
termination between the
differential output pairs. Drive DT low to select no output termination.
33
SLVS/LVDS
Differential Output-Signal Format-Select Input. Drive SLVS/LVDS high to select SLVS outputs.
Drive SLVS/LVDS low to select LVDS outputs.
34
CVDD
Clock Power Input. Connect CVDD to a +1.7V to +3.6V power supply. Bypass CVDD to GND
with a 0.1F capacitor in parallel with a
≥ 2.2F capacitor. Install the bypass capacitors as
close as possible to the device.
35
CLK
Single-Ended CMOS Clock Input
43, 46, 49, 54, 57, 60,
63, 64, 67, 71, 74, 77
OVDD
Output-Driver Power Input. Connect OVDD to a +1.7V to +1.9V power supply. Bypass OVDD to
GND with a 0.1F capacitor as close as possible to the device. Bypass the OVDD power plane
to the GND plane with a bulk
≥ 2.2F capacitor. Connect all OVDD pins to the same potential.
44
OUT7N
Channel 7 Negative LVDS/SLVS Output
45
OUT7P
Channel 7 Positive LVDS/SLVS Output
47
OUT6N
Channel 6 Negative LVDS/SLVS Output
48
OUT6P
Channel 6 Positive LVDS/SLVS Output
52
OUT5N
Channel 5 Negative LVDS/SLVS Output
53
OUT5P
Channel 5 Positive LVDS/SLVS Output
55
OUT4N
Channel 4 Negative LVDS/SLVS Output
56
OUT4P
Channel 4 Positive LVDS/SLVS Output
Pin Description
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