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参数资料
| 型号： | MAX1471EVKIT-315 |
| 厂商： | Maxim Integrated |
| 文件页数： | 20/26页 |
| 文件大小： | 0K |
| 描述： | EVAL KIT FOR MAX1471 315MHZ |
| 其它有关文件： | Automotive Product Guide |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 类型： | 接收器，ASK/FSK |
| 频率： | 315MHz |
| 适用于相关产品： | MAX1471 ~ 315MHz |
| 已供物品： | 板 |
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Table 5. Register Configuration
ADDRESS
DATA
A3 A2 A1 A0
D7
D6
D5
D4
D3
D2
D1
D0
POWER CONFIGURATION (0x0)
0000
LNA_EN
AGC_EN
MIXER_
EN
FSKBB_
EN
FSKPD_
EN
ASKBB_
EN
ASKPD_
EN
SLEEP
CONFIGURATION (0x1)
0001
X
GAIN
SET*
FSKCALL
SB
FSK_
DOUT
ASK_
DOUT
TOFF_
PS1
TOFF_
PS0
DRX_
MODE
CONTROL (0x2)
0010
X
AGC
LOCK
X
X
FSKTRK_ ASKTRK_
EN EN
POL_
CAL_EN
FSK_CAL
_EN
OSCILLATOR FREQUENCY (0x3)
0011
d7
d6
d5
d4
d3
d2
d1
d0
OFF TIMER (upper byte) (0x4)
0100
t15
t14
t13
t12
t11
t10
t9
t8
OFF TIMER (lower byte) (0x5)
0101
t7
t6
t5
t4
t3
t2
t1
t0
CPU RECOVERY TIMER (0x6)
0110
t7
t6
t5
t4
t3
t2
t1
t0
RF SETTLE TIMER (upper byte) (0x7)
0111
t15
t14
t13
t12
t11
t10
t9
t8
RF SETTLE TIMER (lower byte) (0x8)
1000
t7
t6
t5
t4
t3
t2
t1
t0
STATUS REGISTER (read only) (0x9)
1001
LOCK
DET
AGCST
CLK
ALIVE
X
X
X
POL_CAL FSK_CAL
_DONE _DONE
AGC DWELL TIMER (0xA)
1010
X
X
X
dt4
dt3*
dt2*
dt1
dt0*
*Power-up state = 1. All other bits, power-up state = 0.
CPU Recovery Timer (t CPU )
The second timer, t CPU (see Figure 12), is used to delay
the power-up of the MAX1471, thereby providing extra
power savings and giving a CPU the time required to
complete its own power-on sequence. The CPU is sig-
naled to begin powering up when the DIO line is pulled
low by the MAX1471 at the end of t OFF . t CPU then begins
counting down, while DIO is held low by the MAX1471.
At the end of t CPU , the t RF counter begins.
t CPU is an 8-bit timer, configured through register 0x6.
The possible t CPU settings are summarized in Table 11.
The data written to the t CPU register (0x6) is multiplied
by 120μs to give the total t CPU time. On power-up, the
CPU timer register is set to zero and must be written
before using DRX mode.
RF Settle Timer (t RF )
The third timer, t RF (see Figure 12), is used to allow the
RF sections of the MAX1471 to power up and stabilize
before ASK or FSK data is received. t RF begins count-
ing once t CPU has expired. At the beginning of t RF , the
modules selected in the power control register (register
0x0) are powered up with the exception of the peak
detectors and have the t RF period to settle.
20
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