参数资料
型号: MAX1471EVKIT-433
厂商: Maxim Integrated
文件页数: 23/26页
文件大小: 0K
描述: EVAL KIT FOR MAX1471 433MHZ
其它有关文件: Automotive Product Guide
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
类型: 接收器,ASK/FSK
频率: 433MHz
适用于相关产品: MAX1471 ~ 433 MHz
已供物品:
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Table 8. Control Register (Address: 0x2)
BIT ID
X
AGCLOCK
X
BIT NAME
None
AGC lock
None
BIT LOCATION
(0 = LSB)
7
6
5, 4
POWER-UP
STATE
Don’t care
0
FUNCTION
Don’t care.
Locks the LNA gain in its present state.
Don’t care.
FSK peak
Enables the tracking mode of the FSK peak detectors
FSKTRK_EN
detector track
3
0
when FSKTRK_EN = 1. (See the Peak Detector s
enable
ASK peak
section.)
Enables the tracking mode of the ASK peak detectors
ASKTRK_EN
detector track
2
0
when ASKTRK_EN = 1.
enable
(See the Peak Detectors section.)
POL_CAL_EN = 1 starts the polling timer calibration.
POL_CAL_EN
Polling timer
calibration enable
1
0
Calibration of the polling timer is needed when using
the MAX1471 in discontinous receive mode.
POL_CAL_EN resets when calibration completes
properly. (See the Calibration section.)
FSK_CAL_EN
FSK calibration
enable
0
0
FSK_CAL_EN starts the FSK receiver calibration.
FSK_CAL_EN resets when calibration completes
properly. (See the Calibration section.)
Table 9. Status Register (Read Only) (Address: 0x9)
BIT ID
LOCKDET
AGCST
CLKALIVE
X
POL_CAL_DONE
FSK_CAL_DONE
BIT NAME
Lock detect
AGC state
Clock/crystal
alive
None
Polling timer
calibration done
FSK calibration
done
BIT LOCATION
(0 = LSB)
7
6
5
4, 3, 2
1
0
FUNCTION
0 = Internal PLL is not locked so the MAX1471 will not receive data.
1 = Internal PLL is locked.
0 = LNA in low-gain state.
1 = LNA in high-gain state.
0 = No valid clock signal seen at the crystal inputs.
1 = Valid clock at crystal inputs.
Don’t care.
0 = Polling timer calibraton in progress or not completed.
1 = Polling timer calibration is complete.
0 = FSK calibration in progress or not completed.
1 = FSK calibration is compete.
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