参数资料
型号: MAX15005AEVKIT+
厂商: Maxim Integrated Products
文件页数: 9/27页
文件大小: 0K
描述: KIT EVAL FOR MAX15005A
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: DC/DC,步升/步降
输出及类型: 3,隔离
输出电压: 3V,110V,60V
电流 - 输出: 650mA,55mA,12mA
输入电压: 6.5 ~ 16 V
稳压器拓扑结构: 回扫
频率 - 开关: 100kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: MAX15005A
MAX15004A/B/MAX15005A/B
4.5V to 40V Input Automotive
Flyback/Boost/SEPIC Power-Supply Controllers
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NAME
IN
ON/ OFF
OVI
SLOPE
N.C.
RTCT
SGND
SYNC
SS
FB
COMP
CS
REG5
PGND
OUT
V CC
EP
FUNCTION
Input Power Supply. Bypass IN with a minimum 0.1μF ceramic capacitor to PGND.
ON/ OFF Input. Connect ON/ OFF to IN for always-on operation. To externally program the UVLO threshold of the
IN supply, connect a resistive divider between IN, ON/ OFF , and SGND. Pull ON/ OFF to SGND to disable the
controller.
Overvoltage Comparator Input. Connect a resistive divider between the output of the power supply, OVI, and
SGND to set the output overvoltage threshold.
Programmable Slope Compensation Capacitor Input. Connect a capacitor (C SLOPE ) to SGND to set the amount
of slope compensation.
Slope compensation = (2.5 x 10 -9 ) / C SLOPE mV/μs with C SLOPE in farads.
No Connection. Not internally connected.
Oscillator-Timing Network Input. Connect a resistor from RTCT to REG5 and a capacitor from RTCT to SGND to
set the oscillator frequency (see the Oscillator Frequency/External Synchronization section).
Signal Ground. Connect SGND to SGND plane.
External-Clock Synchronization Input. Connect SYNC to SGND when not using an external clock.
Soft-Start Capacitor Input. Connect a capacitor from SS to SGND to set the soft-start time interval.
Internal Error-Amplifier Inverting Input. The noninverting input is internally connected to SS.
Error-Amplifier Output. Connect the frequency compensation network between FB and COMP.
Current-Sense Input. The current-sense signal is compared to a signal proportional to the error-amplifier output
voltage.
5V Low-Dropout Regulator Output. Bypass REG5 with a 1μF ceramic capacitor to SGND.
Power Ground. Connect PGND to the power ground plane.
Gate Driver Output. Connect OUT to the gate of the external n-channel MOSFET.
7.4V Low-Dropout Regulator Output—Driver Power Source. Bypass V CC with 0.1μF and 1μF or higher ceramic
capacitors to PGND.
Exposed Pad (MAX15004A/MAX15005A only). Connect EP to the SGND plane to improve thermal performance.
Do not use the EP as an electrical connection.
Maxim Integrated
9
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