参数资料
型号: MAX15009ATN+T
厂商: Maxim Integrated
文件页数: 17/24页
文件大小: 0K
描述: IC REG LDO 5V/ADJ .3A 56-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
稳压器拓扑结构: 正,固定式或可调式
输出电压: 5V,1.8 V ~ 11 V
输入电压: 5 V ~ 40 V
电压 - 压降(标准): 0.8V @ 300mA
稳压器数量: 1
电流 - 输出: 300mA(最小)
电流 - 限制(最小): 330mA
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 56-WFQFN 裸露焊盘
供应商设备封装: 56-TQFN-EP(8x8)
包装: 带卷 (TR)
Automotive 300mA LDO Regulators with
Switched Output and Overvoltage Protector
Use the following formula to calculate R 4 :
R 4 = V TH_PROT x R TOTAL / V OV
where V TH_PROT is the 1.235V FB_PROT rising threshold
and V OV is the desired overvoltage threshold. R 4 = 124k Ω :
R TOTAL = R 3 + R 4
where R 3 = 1.88M Ω . Use a standard 1.87M Ω resistor.
A lower value for total resistance dissipates more
power, but provides better accuracy and robustness
against external disturbances.
Input Transients Clamping
When the external MOSFET is turned off during an
overvoltage event, stray inductance in the power path
may cause additional input-voltage spikes that exceed
the V DSS rating of the external MOSFET or the absolute
maximum rating for the MAX15009. Minimize stray
inductance in the power path using wide traces and
minimize the loop area included by the power traces
and the return ground path.
For further protection, add a zener diode or transient
voltage suppressor (TVS) rated below the absolute
maximum rating limits (Figure 5).
External MOSFET Selection
Select the external MOSFET with adequate voltage rating,
V DSS , to withstand the maximum expected load-dump
input voltage. The on-resistance of the MOSFET,
R DS(ON) , should be low enough to maintain a minimal
voltage drop at full load, limiting the power dissipation
of the MOSFET.
During regular operation, the power dissipated by the
MOSFET is:
P NORMAL = I LOAD 2 x R DS(ON)
Normally, this power loss is small and is safely handled
by the MOSFET. However, when operating the
MAX15009 in overvoltage limiter mode under pro-
longed or frequent overvoltage events, select an exter-
nal MOSFET with an appropriate power rating.
During an overvoltage event, the power dissipation in
the external MOSFET is proportional to both load cur-
rent and to the drain-source voltage, resulting in high
power dissipated in the MOSFET (Figure 6). The power
dissipated across the MOSFET is:
P OV_LIMITER = V Q1 x I LOAD
where V Q1 is the voltage across the MOSFET’s drain
and source during overvoltage limiter operation, and
I LOAD is the load current.
V MAX
V OV
V IN
IN
V SOURCE
IN
GATE
+ V Q1 -
I LOAD
V SOURCE
TVS
MAX15009
GATE
LOAD
TVS
MAX15009
SOURCE
LOAD
SOURCE
FB_PROT
SGND
Figure 5. Protecting the MAX15009 Input from High-Voltage
Transients
SGND
Figure 6. Power Dissipated Across MOSFETs During an
Overvoltage Fault (Overvoltage Limiter Mode)
______________________________________________________________________________________
17
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