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参数资料
| 型号： | MAX15009ATN+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 18/24页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 5V/ADJ .3A 56-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 稳压器拓扑结构： | 正，固定式或可调式 |
| 输出电压： | 5V，1.8 V ~ 11 V |
| 输入电压： | 5 V ~ 40 V |
| 电压 - 压降（标准）： | 0.8V @ 300mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 300mA（最小） |
| 电流 - 限制（最小）： | 330mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-WFQFN 裸露焊盘 |
| 供应商设备封装： | 56-TQFN-EP（8x8） |
| 包装： | 带卷 (TR) |
Automotive 300mA LDO Regulators with
Switched Output and Overvoltage Protector
Calculate the discharge time, t 1 , using the following
equation:
GATE
t 2
t 1 = C SOURCE ×
0.04 × V OV
I LOAD + I GATEPD
where t 1 is in ms, V OV is the adjusted overvoltage
threshold in volts, I LOAD is the external load current in
mA, and I GATEPD is the 100mA (max) internal pulldown
current of GATE. C SOURCE is the value of the capacitor
SOURCE
t 1
t OVP
t 3
connected between the source of the MOSFET and
PGND in μF.
GATE Delay Time (t 2 )
When SOURCE falls 4% below the overvoltage-threshold
voltage, the internal current sink is disabled and the
Figure 7. MAX15009 Timing Diagram
Overvoltage-Limiter Mode
Switching Frequency
When the MAX15009 is configured in overvoltage-
internal charge pump begins recharging the external
GATE voltage. Due to the external load, the SOURCE
voltage continues to drop until the gate of the MOSFET is
recharged. The time needed to recharge GATE and re-
enhance the external MOSFET is approximately:
limiter mode, the external n-channel MOSFET is subse-
quently switched on and off during an overvoltage
event. The output voltage at OUT_PROT resembles a
t 2 = C iss ×
V GS ( TH ) + V F
I GATE
Δ V 2 = LOAD
periodic sawtooth waveform. Calculate the period of
the waveform, t OVP , by summing three time intervals
(Figure 7):
t OVP = t 1 + t 2 + t 3
where t 1 is the V SOURCE output discharge time, t 2 is the
GATE delay time, and t 3 is the V SOURCE output charge
time.
During an overvoltage event, the power dissipated
inside the MAX15009 is due to the gate pulldown cur-
rent, I GATEPD . This amount of power dissipation is
worse when I SOURCE = 0 (C SOURCE is discharged only
by the internal current sink).
The worst-case internal power dissipation contribution
in overvoltage limiter mode, P OVP , in watts can be
approximated using the following equation:
where t 2 is in μs, C iss is the input capacitance of the
MOSFET in pF, and V GS(TH) is the GATE-to-SOURCE
threshold voltage of the MOSFET in volts. V F is the 0.7V
(typ) internal clamp diode forward voltage of the MOS-
FET in volts, and I GATE is the charge-pump current
45μA (typ). Any external capacitance between GATE
and PGND adds up to C iss .
During t 2 , the SOURCE capacitance, C SOURCE , loses
charge through the output load. The voltage across
C SOURCE , Δ V 2 , decreases until the MOSFET reaches
its V GS(TH) threshold. Approximate Δ V 2 using the fol-
lowing formula:
I × t 2
C SOURCE
P OVP = V OV × 0 . 98 × I GATEPD ×
t 1
t OVP
SOURCE Output Charge Time (t 3 )
Once the GATE voltage exceeds the GATE-to-SOURCE
where V OV is the overvoltage threshold voltage in volts
and I GATEPD is 100mA (max) GATE pulldown current.
Output Discharge Time (t 1 )
When the voltage at SOURCE exceeds the adjusted
overvoltage threshold, GATE ’s internal pulldown is
threshold, V GS(TH) , of the external MOSFET, the MOS-
FET turns on and the charge through the internal
charge pump with respect to the drain potential, Q G ,
determines the slope of the output voltage rise. The
time required for the SOURCE voltage to rise again to
the overvoltage threshold is:
enabled until V SOURCE drops by 4%. The internal cur-
rent sink, I GATEPD , and the external load current,
I LOAD , discharge the external capacitance from
SOURCE to ground.
t 3 =
C rss × Δ V SOURCE
I GATE
18
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| MAX15010ATJ+ | 功能描述:低压差稳压器 - LDO Automotive 300mA w/Tracker Output RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
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