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参数资料
| 型号： | MAX15017BATX+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 12/26页 |
| 文件大小： | 0K |
| 描述： | IC REG DL BCK/LINEAR 36TQFNEP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 拓扑： | 降压（降压）同步（1），线性（LDO）（1） |
| 功能： | 车载 |
| 输出数： | 2 |
| 频率 - 开关： | 500kHz |
| 电压/电流 - 输出 1： | 1.26 V ~ 32 V，1A |
| 电压/电流 - 输出 2： | 5 V ~ 40 V，50mA |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 7.5 V ~ 40 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-WFQFN 裸露焊盘 |
| 供应商设备封装： | 36-TQFN 裸露焊盘（6x6） |
| 包装： | 带卷 (TR) |
1A, 4.5V to 40V Input Buck Converters with
50mA Auxiliary LDO Regulators
Pin Description
PIN
MAX15014/
MAX15017
1, 2, 3, 9, 12,
14, 16, 19, 24,
26, 27, 30, 35
23, 28
MAX15015/
MAX15016
1, 2, 3, 9, 12,
14, 16, 19, 24,
26, 27, 30, 35
—
NAME
N.C.
I.C.
FUNCTION
No Connection. Not internally connected. Leave unconnected or connect to SGND.
Internally Connected. Leave unconnected.
Active-Low Reset Output. When the rising V LDO_OUT voltage crosses the reset
4
4
RESET
threshold, RESET goes high after an adjustable delay. Pull up RESET to LDO_OUT
with at least 4k ? . RESET is an active-low open-drain output.
5
5
SGND
Signal Ground Connection. Connect SGND and PGND together at one point near
the input bypass capacitor negative terminal.
Reset Timeout Delay Capacitor Connection. CT is pulled low during reset. When out
6
6
CT
of reset, CT is pulled up to an internal 3.6V rail with a 2μA current source. When the
rising CT voltage reaches the trip threshold (typically 1.24V), RESET is deasserted.
When EN_SYS is low or in thermal shutdown, CT is low.
Switching Regulator Enable Input (Active High). If EN_SW is high and EN_SYS is
7
7
EN_SW
high, the switching power supply is enabled. EN_SW is internally pulled down to
SGND through a 0.5μA current sink.
Active-High System Enable Input. Connect EN_SYS high to turn on the system. The
8
8
EN_SYS
LDO is active if EN_SYS is high; once EN_SYS is high, the switching regulator can
be turned on if EN_SW is high. EN_SYS is internally pulled down to SGND through a
0.5μA current sink.
LDO Feedback Input/Output Voltage Setting. Connect SET_LDO to SGND to select
10
10
SET_LDO
the preset output voltage (5V or 3.3V). Connect SET_LDO to an external resistor-
divider network for adjustable output operation.
Linear Regulator Output. Bypass with at least 10μF low-ESR capacitor from
11
11
LDO_OUT
LDO_OUT to SGND. In the 5V LDO versions (A), the LDO operates in dropout below
6V down to the UVLO trip point.
13
15
17, 18
20, 21
13
15
17, 18
20, 21
IN_LDO
BST
LX
DRAIN
LDO Input Voltage. The input voltage range for the LDO extends from 5V to 40V.
Bypass with a 0.1μF ceramic capacitor to SGND.
High-Side Gate Driver Supply. Connect BST to the cathode of the bootstrap diode
and to the positive terminal of the bootstrap capacitor.
Source Connection of Internal High-Side Switch. Connect both LX pins to the
inductor and the cathode of the freewheeling diode.
Drain Connection of the Internal High-Side Switch. Connect both DRAIN inputs
together.
Power Ground Connection. Connect the input bypass capacitor negative terminal,
22
22
PGND
the anode of the freewheeling diode, and the output filter capacitor negative terminal
to PGND. Connect PGND to SGND together at a single point near the input bypass
capacitor negative terminal.
12
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