参数资料
型号: MAX15021ATI+
厂商: Maxim Integrated Products
文件页数: 18/24页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ DL 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.6 V ~ 5.5 V
输入电压: 2.5 V ~ 5.5 V
PWM 型: 电压模式
频率 - 开关: 500kHz ~ 4MHz
电流 - 输出: 2A,4A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
包装: 管件
供应商设备封装: 28-TQFN-EP(5x5)
MAX15021
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Tracking/Sequencing Capability
Solving for R 1 :
R 1 [k Ω ] =
R F [k Ω ] × 4 × ESR[m Ω ] × V FB [V]
2 π × f CO [kHz] × L[ μ H] × V OUT_ [V]
R I
V OUT_
R 1
C CF
R F
C F
where V FB is the 0.6V (typ) FB_ input-voltage set-point,
C I
L is the value of the regulator inductor, ESR is the
series resistance of the output capacitor, and V OUT_ is
the desired output voltage.
1) C F is determined from the compensator’s leading
R 2
FB_
V REF
COMP_
zero, f Z1 , and R F as follows:
C F [ μ F] =
1
2 π × R F [k Ω ] × f Z1 [kHz]
Figure 6a. Type III Compensation Network
GAIN
(dB)
2) C CF is determined from the compensator’s high-fre-
quency pole, f P1 , and R F as follows:
( )
C CF [ μ F] =
1
2 π × R F [k Ω ] × f P1 [kHz]
1ST ASYMPTOTE
( ω R 1 C F ) -1
4TH ASYMPTOTE
R F
R I
( )
3) Calculate R 2 using the following equation:
2ND ASYMPTOTE
R F 1
R 1
3RD ASYMPTOTE
( ω R F C I ) -1
5TH ASYMPTOTE
( ω R I C CF ) -1
R 2 1 [k Ω ] ×
[k Ω ] = R
V FB [V]
V OUT_ [V] ? V FB [V]
where V FB = 0.6V (typ) and V OUT_ is the output voltage
of the regulator.
1ST POLE
(AT ORIGIN)
1ST ZERO 2ND POLE
(R F C F ) -1 (R I C I ) -1
2ND ZERO
(R 1 C I ) -1
3RD POLE
(R F C CF ) -1
ω (rad/sec)
Type III: Compensation when f CO < f ESR
As indicated above, the position of the output capaci-
tor’s inherent ESR zero is critical in designing an appro-
priate compensation network. When low-ESR ceramic
output capacitors (MLCCs) are used, the ESR zero fre-
quency (f ESR ) is usually much higher than the desired
crossover frequency (f CO ). In this case, a type III com-
pensation network is recommended (see Figure 6a).
As shown in Figure 6b, the Type III compensation net-
Figure 6b. Type III Compensation Network Response
f P1 introduces a pole at zero frequency (integrator) for
nulling DC output voltage errors.
f P1 = at the origin (0Hz)
Depending on the location of the ESR zero (f ESR ), f P2
can be used to cancel it, or to provide additional atten-
uation of the high-frequency output ripple.
work introduces two zeros and three poles into the con-
trol loop. The error amplifier has a low-frequency pole
at the origin, two zeros, and two higher frequency poles
f P2 =
1
2 π × R I × C I
at the following frequencies:
f P3 attenuates the high-frequency output ripple.
f Z1 =
f Z2 =
f P3 =
2 π × R F × F CF
1
2 π × R F × C F
1
2 π × C I × (R 1 + R I )
Two midband zeros (f Z1 and f Z2 ) are designed to com-
pensate for the pair of complex poles introduced by the
LC filter.
1
2 π × R F × ( C F C CF
Since C CF << C F then:
)
=
f P3 =
1
C × C
C F + C CF
1
2 π × R F × C CF
18
Maxim Integrated
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MAX15021EVKIT+ 功能描述:电源管理IC开发工具 MAX15021 Eval Kit RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V