参数资料
型号: MAX15021ATI+
厂商: Maxim Integrated Products
文件页数: 19/24页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ DL 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.6 V ~ 5.5 V
输入电压: 2.5 V ~ 5.5 V
PWM 型: 电压模式
频率 - 开关: 500kHz ~ 4MHz
电流 - 输出: 2A,4A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
包装: 管件
供应商设备封装: 28-TQFN-EP(5x5)
MAX15021
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Tracking/Sequencing Capability
The locations of the zeros and poles should be such
Solving for C I :
that the phase margin peaks around f CO .
Set the ratios of f CO -to-f Z and f P -to-f CO equal to one anoth-
er, e.g., f CO = f P = 5 is a good number to get approximately
f Z f CO
C I [ pF] =
( 2 π × f CO [kHz] × L[ μ H] × C OUT [ μ F] )
4 × R F [k Ω ]
f CO [kHz] ≤ SW
60° of phase margin at f CO . Whichever technique, it is
important to place the two zeros at or below the double
pole to avoid the conditional stability issue.
The following procedure is recommended:
1) Select a crossover frequency, f CO , at or below one-
tenth the switching frequency (f SW ):
f   [kHz]
10
2) Calculate the LC double-pole frequency, f LC :
6) For those situations where f LC < f CO < f ESR < f SW /2,
as with low-ESR tantalum capacitors, the compen-
sator’s second pole (f P2 ) should be used to cancel
f ESR . This provides additional phase margin. On the
system Bode plot, the loop gain maintains its
+20dB/decade slope up to 1 / 2 of the switching fre-
quency verses flattening out soon after the 0dB
crossover. Then set:
f P2 = f ESR
If a ceramic capacitor is used, then the capacitor ESR
zero, f ESR , is likely to be located even above one-half of
the switching frequency, that is f LC < f CO < f SW /2 <
f LC [MHz] ≈
1
2 π × L[ μ H] × C OUT [ μ F]
f ESR . In this case, the frequency of the second pole
(f P2 ) should be placed high enough not to significantly
erode the phase margin at the crossover frequency.
4) Place the compensator ’s first f Z1 =
where C OUT is the output capacitor of the regulator.
3) Select the feedback resistor, R F , in the range of
3.3k Ω to 30k Ω .
1
zero at or below the output filter’s 2 π × R F × C F
double-pole, f LC , as follows:
For example, f P2 can be set at 5 x f CO , so that its con-
tribution to phase loss at the crossover frequency f CO is
only about 11°:
f P2 = 5 x f CO
Once f P2 is known, calculate R I :
C F [ μ F] =
1
2 π × R F [k Ω ] × 0.5 × f LC [kHz]
R I [k Ω ] =
1
2 π × f P2 [kHz] × C I [ μ F]
5) The gain of the modulator (Gain MOD )—comprised of
the regulator ’s pulse-width modulator, LC filter,
feedback divider, and associated circuitry—at the
7) Place the second zero (f Z2 ) at 0.2 x f CO or at f LC ,
whichever is lower, and calculate R 1 using the fol-
lowing equation:
Gain MOD = 4 ×
crossover frequency is:
1
(2 π × f CO [MHz]) 2 × L[ μ H] × C OUT [ μ F]
R 1 [k Ω ] =
1
2 π × f Z2 [kHz] × C I [ μ F]
The gain of the error amplifier (Gain E/A ) in midband fre-
quencies is:
8) Place the third pole (f P3 ) at 1/2 the switching fre-
quency and calculate C CF from:
Gain E/A = 2 π × f CO [kHz] × C I [ μ F] × R F [k Ω ]
The total loop gain is the product of the modulator gain
C CF [ n F] =
( 2 π × 0.5 × f SW [MHz] × R F [k Ω ] )
1
and the error amplifier gain at f CO should be equal to 1,
as follows:
9) Calculate R 2 as:
(2 π × f CO [kHz]) × C OUT [ μ F] × L[ μ H]
So:
4 ×
Gain MOD x Gain E/A = 1
1
2
R 2 [k Ω ] = R 1 [k Ω ] ×
where V FB = 0.6V (typ).
V FB [V]
V OUT_ [V] ? V FB [V]
× 2 π × f CO [kHz] × C I [ p F] × R F [k Ω ] = 1
Maxim Integrated
19
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MAX15021ATI+T 功能描述:直流/直流开关调节器 Dual 4A/2A 4MHz w/Tracking/Seq RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5
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