参数资料
型号: MAX15021ATI+T
厂商: Maxim Integrated Products
文件页数: 14/24页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ DL 28TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.6 V ~ 5.5 V
输入电压: 2.5 V ~ 5.5 V
PWM 型: 电压模式
频率 - 开关: 500kHz ~ 4MHz
电流 - 输出: 2A,4A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 28-TQFN-EP(5x5)
MAX15021
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Tracking/Sequencing Capability
Δ V ESR [mV]
C OUT [ μ F ] =
Use the following equation to calculate the input ripple
when only one regulator is enabled:
I CIN(RMS) [A] = I LOAD(MAX) [A] ×
V OUT_ [V] × ( V PVIN_ ? V OUT_ ) [V]
V PVIN_ [V]
The MAX15021 includes UVLO hysteresis to avoid possi-
ble unintentional chattering during turn-on. Use additional
bulk capacitance if the input source impedance is high. If
using a lower input voltage, additional input capacitance
put voltage deviation below the tolerable limits of the
electronics being powered.
Use the following equations to calculate the required
output capacitance, ESR, and ESL for minimal output
deviation during a load step:
ESR [ m Ω ] =
I STEP [A]
I STEP [A] × t RESPONSE [ μ s ]
Δ V Q [V]
helps to avoid possible undershoot below the undervolt-
age lockout threshold during transient loading.
ESL [ nH ] =
Δ V ESL [mV] × t STEP [ μ s ]
I STEP [A]
Output-Capacitor Selection
The allowed output-voltage ripple and the maximum
deviation of the output voltage during load steps deter-
mine the required output capacitance and its ESR. The
output ripple is mainly composed of Δ V Q (caused by
the capacitor discharge) and Δ V ESR (caused by the
voltage drop across the equivalent series resistance of
the output capacitor). The equations for calculating the
output capacitance and its ESR are:
where I STEP is the load step, t STEP is the rise time of the
load step, and t RESPONSE is the response time of the
controller.
Compensation-Design Guidelines
The MAX15021 uses a fixed-frequency, voltage-mode
control scheme that regulates the output voltage by
comparing the output voltage against a fixed reference.
The subsequent “error ” voltage that appears at the
C OUT [ μ F ] =
Δ I P ? P [A]
8 × Δ V Q [V] × f SW [MHz]
error-amplifier output (COMP_) is compared against an
internal ramp voltage to generate the required duty
cycle of the pulse-width modulator. A second-order
ESR [ m Ω ] =
2 × Δ V ESR [mV]
Δ I P ? P [A]
lowpass LC filter removes the switching harmonics and
passes the DC component of the pulse-width-modulat-
ed signal to the output. The LC filter has an attenuation
where Δ I P-P is the peak-to-peak inductor current, and
f SW is the switching frequency.
Δ V ESR and Δ V Q are not directly additive since they are
out of phase from each other. If using ceramic capaci-
tors, which generally have low ESR, Δ V Q dominates. If
using electrolytic capacitors, Δ V ESR dominates.
The allowable deviation of the output voltage during
fast load transients also affects the output capacitance,
its ESR, and its equivalent series inductance (ESL). The
output capacitor supplies the load current during a
load step until the controller responds with an
increased duty cycle. The response time (t RESPONSE )
depends on the gain bandwidth of the controller (see
the Compensation-Design Guidelines section). The
resistive drop across the output capacitor ’s ESR
( Δ V ESR ), the drop across the capacitor’s ESL ( Δ V ESL ),
and the capacitor discharge ( Δ V Q ) cause a voltage
droop during the load-step (I STEP ). Use a combination
of low-ESR tantalum/aluminum electrolyte and ceramic
capacitors for better load transient and voltage ripple
performance. Nonleaded capacitors and capacitors in
parallel help reduce the ESL. Keep the maximum out-
14
slope of -40dB/decade and introduces 180° of phase
shift at frequencies above the LC resonant frequency.
This phase shift in addition to the inherent 180° of
phase shift of the regulator’s negative feedback system
turns the feedback into unstable positive feedback. The
error amplifier and its associated circuitry must be
designed to achieve a stable closed-loop system.
The basic controller loop consists of a power modulator
(comprised of the regulator’s pulse-width modulator,
associated circuitry, and LC filter), an output feedback
divider, and an error amplifier. The power modulator has
a DC gain set by V AVIN /V RAMP where the ramp voltage
(V RAMP ) is a function of the V AVIN and results in a fixed
DC gain of 4V/V, providing effective feed-forward com-
pensation of input-voltage supply DC variations. The
feed-forward compensation eliminates the dependency
of the power modulator’s gain on the input voltage such
that the feedback compensation of the error amplifier
requires no modifications for nominal input-voltage
changes. The output filter is effectively modeled as a
double-pole and a single zero set by the output induc-
tance (L), the DC resistance of the inductor (DCR), the
output capacitance (C OUT ) and its equivalent series
resistance (ESR).
Maxim Integrated
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相关代理商/技术参数
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MAX15021EVKIT+ 功能描述:电源管理IC开发工具 MAX15021 Eval Kit RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V
MAX15022ATI+ 功能描述:直流/直流开关调节器 Dual 4A/2A 4MHz w/Dual LDO Ctlr RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5
MAX15022ATI+T 功能描述:直流/直流开关调节器 Dual 4A/2A 4MHz w/Dual LDO Ctlr RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5
MAX15022EVKIT+ 功能描述:电源管理IC开发工具 MAX15022 Eval Kit RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V
MAX15023ETG/V+ 功能描述:DC/DC 开关控制器 4.5-28V Input Dual Out Synch Buck RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK