参数资料
型号: MAX15023ETG/V+
厂商: Maxim Integrated Products
文件页数: 10/28页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 24WQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 75
PWM 型: 电压模式
输出数: 2
频率 - 最大: 1MHz
占空比: 87.5%
电源电压: 4.5 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-WFQFN 裸露焊盘
包装: 管件
MAX15023
Wide 4.5V to 28V Input, Dual-Output
Synchronous Buck Controller
Pin Description (continued)
10
PIN
13
14
15
16
17
18
19
20
21
22
23
24
NAME
PGND2
DL2
PGOOD2
V CC
FB2
COMP2
RT
SGND
IN
LIM2
LIM1
COMP1
EP
FUNCTION
Low-Side Gate-Driver Supply Return (Regulator 2). Connect to the source of the low-side MOSFET of
Regulator 2.
Low-Side Gate-Driver Output for Regulator 2. DL2 swings from V CC to PGND2. DL2 is low before V CC
reaches the UVLO rising threshold voltage.
Power-Good Output (Open Drain) for Channel 2. To obtain a logic signal, pull up PGOOD2 with an external
resistor connected to a positive voltage below 28V.
Internal 5.2V Linear Regulator Output and the Device’s Core Supply. When using the internal regulator,
bypass V CC to SGND with a 4.7μF minimum low-ESR ceramic capacitor. If V CC is connected to IN for 5V
operation, then a 2.2μF ceramic capacitor is adequate for decoupling (see the Typical Application Circuits ).
Feedback Input for Regulator 2. Connect FB2 to a resistive divider between output 2 and SGND to adjust
the output voltage between 0.6V and (0.85 x input voltage (V)). See the Setting the Output Voltage section.
Compensation Pin for Regulator 2. See the Compensation section.
Oscillator-Timing Resistor Input. Connect a resistor from RT to SGND to set the oscillator frequency from
200kHz to 1MHz (see the Setting the Switching Frequency section).
Signal Ground. Connect SGND to the SGND plane. SGND also serves as sensing input of the synchronous
MOSFET’s V DS drop (source terminals) for both channels.
Internal V CC Regulator Input. Bypass IN to SGND with a 1μF minimum ceramic capacitor when the internal
linear regulator (V CC ) is used. When operating in the 5V ±10% range, connect IN to V CC .
Current-Limit Adjustment for Regulator 2. Connect a resistor (R LIM2 ) from LIM2 to SGND to adjust the
current-limit threshold (V ITH2 ) from 30mV (R LIM2 = 6k ? ) to 300mV (R LIM2 = 60k ? ). See the Setting the
Cycle-by-Cycle Low-Side Source Peak Current Limit section.
Current-Limit Adjustment for Regulator 1. Connect a resistor (R LIM1 ) from LIM1 to SGND to adjust the
current-limit threshold (V ITH1 ) from 30mV (R LIM1 = 6k ? ) to 300mV (R LIM1 = 60k ? ). See the Setting the
Cycle-by-Cycle Low-Side Source Peak Current Limit section.
Compensation Pin for Regulator 1. See the Compensation section.
Exposed Paddle. Connect EP to a large copper plane at SGND potential to improve thermal dissipation. Do
not use as the main IC’s SGND ground connection.
Maxim Integrated
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