参数资料
型号: MAX15034BAUI+
厂商: Maxim Integrated Products
文件页数: 19/26页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 28TSSOP-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
PWM 型: 电流模式
输出数: 1 或 2
频率 - 最大: 1MHz
电源电压: 4.75 V ~ 5.5 V,5 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
包装: 管件
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Table 1. High-Side MOSFET Losses
LOSS
DESCRIPTION
Losses associated with MOSFET on-time and
SEGMENT LOSS
P CONDUCTION = I RMS 2 × R DS ( ON )
Conduction Loss
on-resistance. I RMS is a function of load current
and duty cycle.
where I RMS ≈
V OUT
V IN
× I LOAD
Gate Drive Loss
Losses associated with charging and
discharging the gate capacitance of the
MOSFET every cycle. Use the MOSFET’s (Q G )
specification.
Losses during the drain voltage and drain
P GATEDRIVE = V DD × ( Q G ? Q GD ) × f SW
Switching Loss
current transitions for every switching cycle.
Losses occur only during the Q GS2 and Q GD
time period and not during the initial Q GS1
period. The initial Q GS1 period is the rise in the
gate voltage from zero to V TH. R DH_ is the high-
P SWITCH = V IN × I LOA D × f SW ×
(Q GS 2 + Q GD )
I GATE
side MOSFET driver’s on-resistance and R GATE
is the internal gate resistance of the high-side
MOSFET (Q GD and Q GS2 are found in the
MOSFET data sheet).
Losses associated with Q OSS of the MOSFET
where I GATE =
V DD
2 × ( R DH _ + R GATE )
Output Loss
occur every cycle when the high-side MOSFET
turns on. The losses are caused by both
MOSFETs, but are dissipated in the high-side
P OUTPUT =
Q OSS ( HS ) + Q OSS ( LS )
2
× V IN × f SW
MOSFET.
ripple current. A low-ESR input capacitor that can han-
dle the maximum input RMS ripple current of one chan-
nel must be used. The maximum RMS capacitor ripple
current is given by:
step loads determine the capacitance and the ESR
requirements for the output capacitors. The output rip-
ple can be approximated as the inductor current ripple
multiplied by the output capacitor’s ESR (R ESR_OUT ).
The peak-to-peak inductor current ripple is given by:
? I L = OUT
I CIN ( RMS ) ≈ I MAX
V OUT ( V IN ? V OUT )
V IN
V   (1 ? D)
L × f SW
where I MAX is the full load current of the regulator. V OUT
is the output voltage of the same regulator and C IN is C5
in Figure 6. The ESR of the input capacitors wastes
power from the input and heats up the capacitor.
Reducing the ESR is important to maintain a high overall
efficiency and in reducing the heating of the capacitors.
Output Capacitors
The worst-case peak-to-peak inductor ripple current,
the allowable peak-to-peak output ripple voltage, and
the maximum deviation of the output voltage during
During a load step, the allowable deviation of the output
voltage during the fast transient load dictates the output
capacitance and ESR. The output capacitors supply the
load step until the controller responds with a greater duty
cycle. The response time (t RESPONSE ) depends on the
closed-loop bandwidth of the regulator. The resistive
drop across the capacitor’s ESR and capacitor discharge
causes a voltage drop during a load step. Use a combi-
nation of SP polymer and ceramic capacitors for better
transient load and ripple/noise performance.
______________________________________________________________________________________
19
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