参数资料
型号: MAX15041EVKIT+
厂商: Maxim Integrated Products
文件页数: 15/18页
文件大小: 0K
描述: KIT EVAL MAX15041ETE
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
系列: *
Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
For R LOAD much greater than ESR, the equation can be
further simplified as follows:
this third-pole placement is well beyond the desired
crossover frequency, minimizing its interaction with the
R C = ×
V OUT
V FB
2 π × f CO × C OUT
g MV × G MOD
system loop response at crossover. If C CC is smaller than
10pF, it can be neglected in these calculations.
Setting the Soft-Start Time
≤ CO
f Z 1 =
C SS = SS SS
where V FB is equal to 0.606V.
3) Select C C . C C is determined by selecting the
desired first system zero, f Z1 , based on the desired
phase margin. Typically, setting f Z1 below 1/5th of
f CO provides sufficient phase margin.
1 f
2 π × C C R C 5
therefore:
The soft-start feature ramps up the output voltage slow-
ly, reducing input inrush current during startup. Size the
C SS capacitor to achieve the desired soft-start time t SS
using:
I × t
V FB
I SS , the soft-start current, is 5μA (typ) and V FB , the out-
put feedback voltage threshold, is 0.606V (typ). When
using large C OUT capacitance values, the high-side
current limit may trigger during the soft-start period. To
C C ≥
5
2 π × f CO × R C
ensure the correct soft-start time, t SS , choose C SS large
enough to satisfy:
4) If the ESR output zero is located at less than one-half
the switching frequency use the (optional) sec-
ondary compensation capacitor, C CC , to cancel it,
C SS >> C OUT ×
V OUT × I SS
( I HSCL _ MIN ? I OUT ) × V FB
as follows:
I HSCL_MIN is the minimum high-side switch, current-
1
2 π × C CC R C
therefore:
= f P 3 = f Z 2 =
1
2 π × C OUT ESR
limit value.
Power Dissipation
The MAX15041 is available in a thermally enhanced
TQFN package and can dissipate up to 1.666W at T A =
+70°C. The exposed pad should be connected to
C CC =
C OUT × ESR
R C
SGND externally, preferably soldered to a large ground
plane to maximize thermal performance. When the die
temperature exceeds +155°C, The thermal-shutdown
If the ESR zero exceeds 1/2 the switching frequency,
use the following equation:
protection is activated (see the Thermal-Shutdown
Protection section).
= SW
therefore:
f P 3 =
1
2 π × C CC R C
f
2
Layout Procedure
Careful PCB layout is critical to achieve clean and sta-
ble operation. It is highly recommended to duplicate
the MAX15041 evaluation kit layout for optimum perfor-
mance. If deviation is necessary, follow these guide-
lines for good PCB layout:
C CC =
2
2 π × f SW × R C
1) Connect input and output capacitors to the power
ground plane; connect all other capacitors to the
signal ground plane.
The downside of C CC is that it detracts from the overall
system phase margin. Care should be taken to guarantee
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