参数资料
型号: MAX15049EVKIT+
厂商: Maxim Integrated
文件页数: 26/31页
文件大小: 0K
描述: EVAL KIT FOR MAX15049
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 3,非隔离
输出电压: 1.2V,1.8V,3.3V
电流 - 输出: 6A,3A,3A
输入电压: 5 V ~ 16 V
稳压器拓扑结构: 降压
频率 - 开关: 500kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: MAX15049
MAX15048/MAX15049
Triple-Output Buck Controllers
with Tracking/Sequencing
f CO ≤ SW
f LC =
Type III: Compensation when f CO < f ZERO, ESR
As previously indicated, the position of the output capac-
itor’s inherent ESR zero is critical in designing an appro-
priate compensation network. When low-ESR ceramic
output capacitors are used, the ESR zero frequency
(f ZERO, ESR ) is usually much higher than unity crossover
frequency (f CO ). In this case, a Type III compensation
network is recommended (see Figure 6a).
As shown in Figure 6b, Type III compensation network
introduces two zeros and three poles into the control
Use the following procedure to calculate the compensa-
tion network components:
1) Select a crossover frequency, f CO :
f
10
2) Calculate the LC double-pole frequency, f LC :
1
2 π × L × C OUT
=
f Z1
loop. The error amplifier has a low-frequency pole at
the origin, two zeros, and higher frequency poles. The
locations of the zeros and poles should be such that the
phase margin peaks at f CO .
Set the ratios of f CO -to-f Z and f P -to-f CO equal to five:
3) Select R F R 10k I .
4) Place a zero:
1
2 π × R F × C F
at 0.75 × f LC
? f CO f P ?
? f Z CO
?
C F =
2 π × f C O × L × C OUT × V RAMP
C I =
? = = 5 ?
f
to get approximately 60° of phase margin at f CO .
Whichever technique is used, it is important to place the
two zeros at or below the double pole to avoid the con-
ditional stability issue.
V OUT_ C CF
where:
1
2 π × R F × 0.75 × f LC
5) Calculate C I for a target unity-gain crossover frequency,
f C :
V IN × R F
R I
C I
R 1
R 2
V REF
R F
g M
C F
COMP
Note: C I is derived by setting the total loop gain at cross-
over frequency to unity, e.g. G E/A (f CO ) x G MOD (f CO ) =
1V/V. The total loop gain can be expressed logarithmi-
cally as follows:
? ?
20 × log 10 ? 2 × π × f CO × R F × C I ? +
G MOD(DC)
20 × log 10 ? ? =
? 2 × π× f
( ? ? ?
CO ) × L × C OUT
Figure 6a. Type III Compensation Network
? ?
2
GAIN
(dB)
6) Place a second zero, f Z2 , at or below f LC , thereby
determining R 1 :
R 1 =
7) Place a pole ( f P1 =
) at or below f ZERO, ESR :
R I =
3RD ASYMPTOTE
ω R F C I
1ST ASYMPTOTE
( ω R I C F ) -1
2ND ASYMPTOTE
( R F R I ) -1
4TH ASYMPTOTE
R F R I-1
5TH ASYMPTOTE
( ω R I C CF ) -1
1
2 π × f Z2 × C I
1
2 π × R I × C I
1
2 π × f ZERO, ESR × C I
1ST POLE
(AT ORIGIN)
1ST ZERO 2ND POLE
(R F C F ) -1 2ND ZERO (R I C I ) -1
(R I C I ) -1
3RD POLE
(R F C CF ) -1
ω( rad/s)
Figure 6b. Type III Compensation Network Response
26
Maxim Integrated
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