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| 型号： | MAX15054AUT+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 7/9页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DVR HIGH SIDE SOT-23-6 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 配置： | 高端 |
| 输入类型： | 非反相 |
| 延迟时间： | 11ns |
| 电流 - 峰： | 2A |
| 配置数： | 1 |
| 输出数： | 1 |
| 高端电压 - 最大（自引导启动）： | 65V |
| 电源电压： | 4.6 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-6 |
| 供应商设备封装： | SOT-6 |
| 包装： | 带卷 (TR) |
High-Side MOSFET Driver for HB LED Drivers
and DC-DC Applications
Undervoltage Lockout
The MAX15054 drives an external high-side MOSFET.
Both the high- and low-side supplies feature separate
UVLO protection that monitors each driver’s input supply
voltage (BST-LX and V DD ). The low-side supply UVLO
threshold (V DD_UVLO ) is referenced to GND and pulls
the driver output low when V DD falls below 4V (typ)
irrespective of the high-side UVLO condition.
The high-side driver UVLO threshold (V BST_UVLO ) is
referenced to LX, and pulls HDRV low when V BST falls
below 3.6V (typ) with respect to LX. After the MAX15054 is
first energized (V DD > V DD_UVLO ), the bootstrap capacitor
(C BST ) between BST and LX is not charged, and HDRV
does not switch since the BST-to-LX voltage is below
V BST_UVLO . An internal charging circuit charges the
BST-LX supply through an external Schottky diode and
within a short time C BST charges through V DD and causes
V BST to exceed V BST_UVLO . HDRV then starts switching
and follows HI. The hysteresis is 0.2V (typ) for both UVLO
thresholds.
Output Driver
The MAX15054 driver contains low on-resistance
p-channel and n-channel devices in a totem pole
configuration for the driver output stage. This allows for
rapid turn-on and turn-off of high gate-charge (Qg)
external switching MOSFETs. The driver exhibits low
drain-to-source resistance (R DS(ON) ) that decreases for
lower operating temperatures. Lower R DS(ON) means
higher source and sink currents from the device as
the external MOSFET gate capacitance charges and
discharges at a quicker rate, resulting in faster switching
speeds. The peak source and sink current provided by
the driver is 2.5A (typ).
Propagation delay from the logic input (HI) to the driver
output is 12ns (typ) ( Figure 1 ). The internal driver also
contains break-before-make logic to eliminate shoot-
through conditions that cause unnecessarily high
operating supply currents, efficiency reduction, and
voltage spikes at V DD .
Voltage from HDRV to LX is approximately equal to V DD
minus the diode drop of the bootstrap diode when in a
high state, and zero when in a low state.
Bootstrap Diode
Connect an external Schottky diode between V DD and
BST, in conjunction with an external bootstrap capacitor
(C BST ), to provide the voltage required to turn on the
MOSFET (see the Typical Operating Circuits ). The diode
charges the bootstrap capacitor from V DD when the
high-side switch is off, and isolates V DD when HDRV is
pulled high when the driver turns on.
Bootstrap Capacitor
The bootstrap capacitor (C BST ) between BST and LX is
used to ensure adequate charge is available to switch
the high-side MOSFET. This capacitor is charged from
V DD by an external bootstrap diode when the MOSFET
is off. The bootstrap capacitor value should be selected
carefully to avoid oscillations during turn-on and turn-
off at the HDRV output. Choose a capacitor value at
least 20 times greater than the total gate capacitance
of the MOSFET being switched. Use a low-ESR ceramic
capacitor (typically a minimum 0.1 F F is needed). The
high-side MOSFET’s continuous on-time is limited due
to the charge loss from the high-side driver’s quiescent
current. The maximum on-time is dependent on the size
of C BST , I BST (125 F A, max), and V BST_UVLO .
Driver Logic Input (HI)
The MAX15054 features a 5V CMOS logic input. The
required logic-input levels are independent of V DD and
are capable of withstanding up to 13.5V. For example,
the MAX15054 can be powered by a 5V supply while the
logic inputs are provided from 12V logic. Additionally, HI
is protected against voltage spikes up to 15V, regardless
of the V DD voltage. The logic input has 900mV hysteresis
to avoid double pulsing during signal transition. The logic
input is a high-impedance input (300k I , typ) and should
not be left unconnected to ensure the input logic state is
at a known level. With the logic input unconnected, HDRV
pulls low as V DD rises above the UVLO threshold. The
PWM output from the controller must assume a proper
state while powering up the device.
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