参数资料
型号: MAX15102EWL+T
厂商: Maxim Integrated
文件页数: 6/10页
文件大小: 0K
描述: IC REG LDO ADJ 2A 15WLP
标准包装: 2,500
稳压器拓扑结构: 正,可调式
输出电压: 0.6 V ~ 5.2 V
输入电压: 1.7 V ~ 5.5 V
电压 - 压降(标准): 0.05V @ 2A
稳压器数量: 1
电流 - 输出: 2A
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 15-WFBGA, WLBGA
供应商设备封装: 15-WLP (2.65x1.57)
包装: 带卷 (TR)
MAX15102
Small 2A, Low-Dropout Linear Regulator
in a 2.7mm x 1.6mm Package
Bump Configuration
TOP VIEW
MAX15102
1
2
3
4
5
+
A
EN
PG
GND
SS_BYP
FB
B
IN
IN
IN
IN
IN
C
OUT
OUT
OUT
OUT
OUT
WLP
Bump Description
BUMP
A1
A2
A3
A4
A5
B1, B2, B3,
B4, B5
C1, C2, C3,
C4, C5
NAME
EN
PG
GND
SS_BYP
FB
IN
OUT
FUNCTION
Active-High Enable Input. Drive EN logic-high to enable the LDO. Connect to IN for always-on
operation.
Power-Good Output. Open-drain output asserts high when the voltage is within regulation.
Ground
SS_BYP Bypass/Soft-Start Input. Connect a ceramic capacitor from SS_BYP to GND to reduce the
output noise and set the soft-start ramp time.
Feedback Input. Connect a resistive divider from OUT to GND to set the output voltage.
Supply Voltage Input. Connect to supply voltage from 1.7V to 5.5V. Bypass IN to GND with a 2.2 F F
or greater ceramic capacitor.
Regulated Output. Connect a 22 F F capacitor from OUT to GND. For better load transient
performance a larger capacitor can be used.
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