参数资料
型号: MAX15102EWL+T
厂商: Maxim Integrated
文件页数: 9/10页
文件大小: 0K
描述: IC REG LDO ADJ 2A 15WLP
标准包装: 2,500
稳压器拓扑结构: 正,可调式
输出电压: 0.6 V ~ 5.2 V
输入电压: 1.7 V ~ 5.5 V
电压 - 压降(标准): 0.05V @ 2A
稳压器数量: 1
电流 - 输出: 2A
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 15-WFBGA, WLBGA
供应商设备封装: 15-WLP (2.65x1.57)
包装: 带卷 (TR)
MAX15102
Small 2A, Low-Dropout Linear Regulator
in a 2.7mm x 1.6mm Package
Input-Output (Dropout) Voltage
A regulator’s minimum input-to-output voltage differential
(dropout voltage) determines the lowest usable supply
voltage. The dropout voltage is simply the product of
regulator’s R DS(ON) for the pass device and rated load
current. The MAX15102‘s R DS(ON) is 25m I , at 2A this
yields a dropout voltage of 50mV (see the Electrical
Characteristics and the Dropout Voltage vs. Output
Current graph in the Typical Operating Characteristics ).
Noise, PSRR, and Transient Response
The MAX15102 is designed to achieve low dropout
voltage while still maintaining good noise, transient
response, and AC rejection. When operating from very
noisy sources, supply noise rejection and transient
response can be improved by increasing the values of
the input and output capacitors. The MAX15102 output
noise is typically 15 F V RMS (see the Noise Density graph
in the Typical Operating Characteristics ).
Thermal Considerations
in PCB Layout
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX15102EWL+ -40 N C to +85 N C 15 WLP
+ Denotes a lead(Pb)-free/RoHS-compliant package.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages . Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE PACKAGE OUTLINE LAND
The rated package dissipation strongly depends on the
copper area connected to the regulator. The maximum
power dissipation allowed in the package is 1538mW
(measured from the MAX15102 EV kit).
TYPE
15 WLP
CODE
W151B2+1
NO.
PATTERN NO.
Refer to
Application
Note 1891
More power dissipation can be handled by the package
if great attention is given during PCB layout. For example,
using the top and bottom copper as a heatsink and
connecting the thermal vias to one of the middle layers
(GND) transfers the heat from the package into the board
more efficiently, resulting in lower junction temperature at
high power dissipation in some MAX15102 applications.
Furthermore, the solder mask around the IC area on both
top and bottom layers can be removed to radiate the heat
directly into the air. The maximum allowable power dis-
sipation in the IC is as follows:
P MAX = [(T J(MAX) - T A )/( B JA )]
where (T J(MAX) - T A ) is the temperature difference
between the maximum-allowed die junction (+150 N C)
and the surrounding air.
A sample layout is available on the MAX15102 EV kit.
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