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参数资料
| 型号： | MAX15112EWG+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 14/23页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 12A 24WLP |
| 产品培训模块： | Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 5.17 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 12A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFBGA，WLBGA |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 24-WLP（3x2） |
MAX15112
High-Efficiency, 12A, Current-Mode Synchronous
Step-Down Regulator with Integrated Switches
I L_PK LOAD +
= I
? I L(P-P) < min (18A, I L_SAT )
( V IN ? V OUT )
V OUT
? I L(P-P) =
Applications Information
Setting the Output Voltage
The MAX15112 output voltage is adjustable from 0.6V
up to 94% of V IN by connecting FB to the center tap of
a resistor-divider between the output and GND (see the
Typical Operating Circuits ). Choose R1 and R2 values
where:
1
2
x
L x f SW
V IN
R1=R2 × ? ? ( V OUT FB ) -1 ? ?
× OUT
C IN =
V OUT
× ? 1- OUT ?
L =
?
? ? V
? ? OUT IN OUT ) ? ?
× ( V - V
I RMS = ? × I LOAD
V IN
so that the DC errors due to the FB input bias current
( Q 500nA) do not affect the output voltage accuracy.
With lower value resistors the DC error is reduced, but
the amount of power consumed in the resistor-divider
increases. R2 values between 1k I and 20k I are accept-
able (see Table 1 for typical values). Once R2 is chosen,
calculate R1 using:
/V
where the feedback threshold voltage V FB = 0.6V (typ).
When regulating for an output of 0.6V in skip mode, short
FB to OUT and keep R2 connected from FB to GND.
Inductor Selection
A high-valued inductor results in reduced inductor-ripple
current, leading to a reduced output-ripple voltage.
However, a high-valued inductor results in either a larger
physical size or a high series resistance (DCR) and a
lower saturation current rating. Typically, choose an
inductor value to produce a current ripple, D I L , equal to
30% of load current. Choose the inductor with the follow-
ing formula:
? V ?
f SW × LIR × I LOAD V IN ?
where f SW is the fixed 1MHz switching frequency, and
LIR is the desired inductor current ratio (typically 0.3). In
addition, the peak inductor current, I L_PK , must always
be below the 18A high-side current-limit and the inductor
saturation current rating, I L_SAT . Ensure that the following
relationship is satisfied:
Input Capacitor Selection
For a step-down converter, the input capacitor, C IN ,
helps to keep the DC input voltage steady, in spite of
discontinuous input AC current. Use low-ESR capacitors
to minimize the voltage ripple due to ESR.
Size C IN using the following formula:
I LOAD V
f SW × ? V IN_RIPPLE V IN
where D V IN_RIPPLE is the maximum-allowed input-ripple
voltage across the input capacitors and is recommend-
ed to be less than 2% of the minimum input voltage,
f SW is the switching frequency (1MHz), and I LOAD is the
output load. The impedance of the input capacitor at
the switching frequency should be less than that of the
input source so high-frequency switching currents do not
pass through the input source, but are instead shunted
through the input capacitor.
Ensure that the input capacitor can accommodate the
input-ripple current requirement imposed by the switch-
ing currents. The RMS input-ripple current is given by:
? ?
12 ?
? ?
? ?
where I RMS is the input RMS ripple current.
Use multiple capacitors in parallel to meet the RMS cur-
rent rating requirement.
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