参数资料
型号: MAX15112EWG+T
厂商: Maxim Integrated Products
文件页数: 17/23页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 12A 24WLP
产品培训模块: Obsolescence Mitigation Program
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 5.17 V
输入电压: 2.7 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 1MHz
电流 - 输出: 12A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-WFBGA,WLBGA
包装: 带卷 (TR)
供应商设备封装: 24-WLP(3x2)
MAX15112
High-Efficiency, 12A, Current-Mode Synchronous
Step-Down Regulator with Integrated Switches
V OUT
V COMP ? I L ?
? G MOD ?
Compensation Design Guidelines
The MAX15112 uses a fixed-frequency, peak current-
mode control scheme to provide easy compensation
and fast transient response. The inductor peak current
is monitored on a cycle-by-cycle basis and compared to
the COMP voltage (output of the voltage error amplifier).
The regulator’s duty cycle is modulated based on the
inductor’s peak current value. This cycle-by-cycle con-
trol of the inductor current emulates a controlled current
source. As a result, the inductor’s pole frequency is shift-
ed beyond the gain bandwidth of the regulator. System
stability is provided with the addition of a simple series
capacitor-resistor from COMP to GND. This pole-zero
combination serves to tailor the desired response of the
closed-loop system. The basic regulator loop consists of
a power modulator (composed of the regulator’s pulse-
width modulator, compensation ramp, control circuitry,
MOSFETs, and inductor), the capacitive output filter and
load, an output feedback divider, and a voltage-loop
error amplifier with its associated compensation circuitry.
See Figure 2 for a graphical representation. The power
modulator’s transfer function with respect to V COMP is:
R LOAD × I L
= = R LOAD × G MOD
? ?
? ?
where I L is the average inductor current, G MOD is the
power modulator’s transconductance, and R LOAD is the
equivalent load resistance value.
FEEDBACK
DIVIDER
V OUT
ERROR AMPLIFIER
POWER MODULATOR
COMPENSATION
V IN
RAMP
OUTPUT FILTER
AND LOAD
R1
*C FF
FB
C
g MC
V FB
COMP
Q HS
I L
V OUT
V COMP
CONTROL
LOGIC
L
DCR
I OUT
R2
g M
R OUT
R C
PWM
COMPARATOR
Q LS
ESR
R LOAD
C OUT
C C
V COMP
G MOD
V OUT
I L
REF
R OUT =
10
AVEA(dB)/20
g M
NOTE: THE G MOD STAGE SHOWN ABOVE MODELS THE AVERAGE CURRENT OF THE INDUCTOR, I L ,
INJECTED INTO THE OUTPUT LOAD, I OUT , e.g., I L = I OUT .
SUCH CAN BE USED TO SIMPLIFY/MODEL THE MODULATION/CONTROL/POWER STAGE
CIRCUITRY SHOWN WITHIN THE BOXED AREA.
*C FF IS OPTIONAL, DESIGNED TO EXTEND THE REGULATOR’S
GAIN BANDWIDTH AND INCREASED PHASE MARGIN FOR SOME
LOW-DUTY CYCLE APPLICATIONS.
Figure 2. Peak Current-Mode Regulator Transfer Model
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