参数资料
| 型号： | MAX1515ETG+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 21/24页 |
| 文件大小： | 0K |
| 描述： | IC REG DDR LV 24-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 转换器，DDR |
| 输入电压： | 1.3 V ~ 3.6 V |
| 输出数： | 2 |
| 输出电压： | 0.5 V ~ 2.7 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 供应商设备封装： | 24-TQFN-EP（4x4） |
| 包装： | 带卷 (TR) |
Low-Voltage, Internal Switch,
Step-Down/DDR Regulator
With the additional capacitance, the REFIN voltage
V CC
R1
C REFIN
SKIP
REF
MAX1515
LX
FB
PGND
L
V OUT
C OUT
slews between the two set points with a time constant
given by R EQ x C REFIN , where R EQ is the equivalent
parallel resistance seen by the slew capacitor.
Referring to Figure 7, the time constant for a positive
REFIN voltage transition is:
REFIN
GND
? R 1 × ( R 2 + R 3 ) ?
? R 1 + R 2 + R 3 ?
R2
MODE
FBSEL0
τ POS = ? ? C REFIN
V OUT(LOW)
V OUT(HIGH)
R3
FBSEL1
and the time constant for a negative REFIN voltage
transition is:
τ POS = ?
? R 1 + R 2 ?
V OUT ( LOW ) = V REF ?
? R 1 + R 2 ?
V OUT ( HIGH ) = V REF ?
? R 1 + R 2 + R 3 ?
Figure 7. Dynamic Output Voltages
voltage-divider network at REFIN. The resulting output
voltages are determined by the following equations:
? R 2 ?
?
? R 2 + R 3 ?
?
Forced-PWM operation is required to ensure fast, accu-
rate negative voltage transitions when REFIN is low-
ered. Since forced-PWM operation disables the
zero-crossing comparator, the inductor current can
reverse under light loads, quickly discharging the out-
put capacitors.
For a step voltage change at REFIN, the rate-of-change
of the output voltage is limited by the inductor current
ramp, the total output capacitance, the current limit,
and the load during the transition. The inductor current
ramp is limited by the voltage across the inductor and
the inductance. The total output capacitance deter-
mines how much current is needed to change the out-
put voltage. Additional load current slows down the
output-voltage change during a positive REFIN voltage
change, and speeds up the output-voltage change dur-
ing a negative REFIN voltage change. Increasing the
current-limit setting speeds up a positive output-voltage
change.
To avoid tripping the power-good comparators, the ref-
erence-voltage slew rate must be slow enough that the
output voltage (V OUT ) can accurately track the refer-
ence voltage (V REFIN ). Add a capacitor across REFIN
and GND to control the rate-of-change of the REFIN
voltage during dynamic transitions and filter noise.
? R 1 × R 2 ?
? C REFIN
PC Board Layout Guidelines
Good layout is necessary to achieve the intended out-
put power level, high efficiency, and low noise. Good
layout includes the use of a ground plane, careful com-
ponent placement, and correct routing of traces using
appropriate trace widths. Refer to the MAX1515 EV kit
for a reference of a good layout.
The following points are in order of decreasing impor-
tance:
1) Minimize switched-current and high-current ground
loops. Connect the input capacitor’s ground, the
output capacitor’s ground, and PGND at a single
point. Connect the resulting island to GND at only
one point.
2) Connect the input filter capacitor less than 5mm
away from IN. The connecting copper trace carries
large currents and must be at least 1mm wide,
preferably 2.5mm.
3) Place the LX node components as close together
and as near to the device as possible. This reduces
noise, resistive losses, and switching losses.
4) A ground plane is essential for optimal perfor-
mance. In most applications, the circuit is located
on a multilayer board, and full use of the four or
more layers is recommended. Use the top and bot-
tom layers for interconnections and the inner layers
for an uninterrupted ground plane. Avoid large AC
currents through the ground plane.
Chip Information
TRANSISTOR COUNT: 8258
PROCESS: BiCMOS
______________________________________________________________________________________
21
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