参数资料
型号: MAX1518BETJ+
厂商: Maxim Integrated Products
文件页数: 16/25页
文件大小: 0K
描述: IC DC-DC CONV TFT-LCD 32-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
应用: 转换器,TFT,LCD
输入电压: 2.6 V ~ 6.5 V
输出数: 1
输出电压: 2.6 V ~ 13 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 管件
TFT-LCD DC-DC Converter with
Operational Amplifiers
Undervoltage Lockout (UVLO)
The undervoltage-lockout (UVLO) circuit compares the
input voltage at IN with the UVLO threshold (2.5V rising,
2.30V falling, typ) to ensure the input voltage is high
enough for reliable operation. The 200mV (typ) hysteresis
prevents supply transients from causing a restart. Once
the input voltage exceeds the UVLO rising threshold,
startup begins. When the input voltage falls below the
UVLO falling threshold, the controller turns off the main
step-up regulator, turns off the linear-regulator outputs,
and disables the switch control block; the operational-
amplifier outputs are high impedance.
Reference Voltage (REF)
2.5V
1.05V
V IN
V REF
V MAIN
V GON
The reference output is nominally 1.25V and can
source at least 50μA (see the Typical Operating
12ms
1.25V
V GOFF
V DEL
Characteristics ). Bypass REF with a 0.22μF ceramic
capacitor connected between REF and AGND.
INPUT SOFT- SOFT-
VOLTAGE START START
SWITCH
CONTROL
Power-Up Sequence and Soft-Start
OK
BEGINS ENDS
ENABLED
Once the voltage on IN exceeds approximately 1.7V,
the reference turns on. With a 0.22μF REF bypass
capacitor, the reference reaches its regulation voltage
of 1.25V in approximately 1ms. When the reference
voltage exceeds 1.0V, the ICs enable the main step-up
regulator, the gate-on linear-regulator controller, and
the gate-off linear-regulator controller simultaneously.
The IC employs soft-start for each regulator to minimize
inrush current and voltage overshoot and to ensure a
well-defined startup behavior. During the soft-start, the
main step-up regulator directly limits the peak inductor
Figure 6. Power-Up Sequence
1.25V (typ), the switch-control block is enabled as
shown in Figure 6. After the switch-control block is
enabled, COM can be connected to SRC or DRN
through the internal p-channel switches, depending
upon the state of CTL. Before startup and when IN is
less than V UVLO , DEL is internally connected to AGND
to discharge C DEL . Select C DEL to set the delay time
using the following equation:
current. The current-limit level is increased through the
soft-start period from zero up to the full current-limit
value in eight equal current steps (ILIM / 8). The maxi-
C DEL = DELAY _ TIME ×
5 μ A
1 . 25 V
mum load current is available after the output voltage
reaches regulation (which terminates soft-start), or after
the soft-start timer expires. Both linear-regulator con-
trollers use a 7-bit soft-start DAC. For the gate-on linear
regulator, the DAC output is stepped in 128 steps from
zero up to the reference voltage. For the gate-off linear
regulator, the DAC output steps from the reference
down to 250mV in 128 steps. The soft-start duration is
14ms (typ) for all three regulators.
A capacitor (C DEL ) from DEL to AGND determines the
switch-control-block startup delay. After the input volt-
age exceeds the UVLO threshold (2.5V typ) and the
soft-start routine for each regulator is complete and
there is no fault detected, a 5μA current source starts
charging C DEL . Once the capacitor voltage exceeds
Switch-Control Block
The switch-control input (CTL) is not activated until all
four of the following conditions are satisfied: the input
voltage exceeds V UVLO , the soft-start routine of all the
regulators is complete, there is no fault condition detect-
ed, and V DEL exceeds its turn-on threshold. Once acti-
vated and if CTL is high, the 5 ? internal p-channel
switch (Q1) between COM and SRC turns on and the
30 ? p-channel switch (Q2) between DRN and COM
turns off. If CTL is low, Q1 turns off and Q2 turns on.
16
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