参数资料
型号: MAX16008TP+T
厂商: Maxim Integrated Products
文件页数: 11/13页
文件大小: 0K
描述: IC VOLT-DET QUAD WINDOW 20TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 多压监控器
监视电压数目: 4
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小 <1 ms
电压 - 阀值: 可调节/可选择
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-WFQFN 裸露焊盘
供应商设备封装: 20-TQFN-EP(4x4)
包装: 带卷 (TR)
Low-Voltage, High-Accuracy, Quad Window
Voltage Detectors in Thin QFN
C SRT ( F ) =
?
?
? ?
(V OH ). Resistor values of 50k Ω to 200k Ω can generally
be used.
RESET Output (MAX16009 Only)
RESET asserts low when the voltage on any of the
UVIN_ inputs falls below its respective threshold, the
voltage on any of the OVIN_ inputs goes above its
respective threshold, or MR is asserted. RESET
remains asserted for the reset timeout period after all
monitored UVIN_ inputs exceed their respective thresh-
olds, all OVIN_ inputs fall below their respective thresh-
olds, and MR is deasserted (see Figure 6). This
open-drain output has a 30μA internal pullup.
Reset Timeout Capacitor
The reset timeout period can be adjusted to accommo-
date a variety of microprocessor (μP) applications from
50μs to 1.12s. Adjust the reset timeout period (t RP ) by
connecting a capacitor (C SRT ) between SRT and GND.
Calculate the reset timeout capacitor as follows:
t RP ( s )
? V TH _ SRT ?
I SRT
Do not use capacitor (C SRT ) values higher than 390nF.
Connect SRT to V CC for a factory-programmed reset
timeout of 140ms (min).
Manual Reset Input ( MR ) (MAX16009 Only)
Many μP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic-low on MR
asserts RESET low. RESET remains asserted while MR
is low, and during the reset timeout period (140ms min)
after MR returns high. The MR input has an internal
20k Ω pullup resistor to V CC , so it can be left open if it is
not used. MR can be driven with TTL or CMOS-logic
levels, or with open-drain/collector outputs. Connect a
normally open momentary switch from MR to GND to
create a manual reset function; external debounce cir-
cuitry is not required. If MR is driven from long cables
or if the device is used in a noisy environment, connect-
ing a 0.1μF capacitor from MR to GND provides addi-
tional noise immunity.
Margin Output Disable ( MARGIN )
MARGIN allows system-level testing while power sup-
plies are adjusted from their nominal voltages. Drive
MARGIN low to deassert all outputs ( UVOUT_ ,
UVIN_
V TH_
V TH_ + V TH_HYS
V CC = 3.3V
5V
100k Ω
RESET
10%
90%
V CC
UVOUT_
RESET
V CC
UVOUT_
t RD
t RP
90%
10%
MAX16008/
MAX16009
V TH_
OVIN_
t D
t D
V TH_ - V TH_HYS
GND
GND
OVOUT_
t D
10%
t D
90%
Figure 5. Interfacing to a Different Logic Supply Voltage
Figure 6. Output Timing Diagram
______________________________________________________________________________________
11
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