参数资料
型号: MAX16008TP+T
厂商: Maxim Integrated Products
文件页数: 7/13页
文件大小: 0K
描述: IC VOLT-DET QUAD WINDOW 20TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 多压监控器
监视电压数目: 4
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小 <1 ms
电压 - 阀值: 可调节/可选择
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-WFQFN 裸露焊盘
供应商设备封装: 20-TQFN-EP(4x4)
包装: 带卷 (TR)
Low-Voltage, High-Accuracy, Quad Window
Voltage Detectors in Thin QFN
Pin Description (continued)
PIN
NAME
FUNCTION
Active-Low Undervoltage Output 2. When the voltage at UVIN2 falls below its threshold, UVOUT2
13
16
UVOUT2
asserts low and stays asserted until the voltage at UVIN2 exceeds its threshold. The open-drain
output has a 30μA internal pullup to V CC .
Active-Low Overvoltage Output 1. When the voltage at OVIN1 rises above its threshold, OVOUT1
14
17
OVOUT1
asserts low and stays asserted until the voltage at OVIN1 falls below its threshold. The open-drain
output has a 30μA internal pullup to V CC .
Active-Low Undervoltage Output 1. When the voltage at UVIN1 falls below its threshold, UVOUT1
15
18
UVOUT1
asserts low and stays asserted until the voltage at UVIN1 exceeds its threshold. The open-drain
output has a 30μA internal pullup to V CC .
16
17
18
19
20
21
22
23
5
12
UVIN1
OVIN1
UVIN2
OVIN2
N.C.
MR
Undervoltage Threshold Input 1. When the voltage on UVIN1 falls below its threshold, UVOUT1
asserts low.
Overvoltage Threshold Input 1. When the voltage on OVIN1 rises above its threshold, OVOUT1
asserts low.
Undervoltage Threshold Input 2. When the voltages on UVIN2 falls below its threshold, UVOUT2
asserts low.
Overvoltage Threshold Input 2. When the voltage on OVIN2 rises above its threshold, OVOUT2
asserts low.
Not Internally Connected
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset
timeout period after MR is deasserted. MR is pulled up to V CC through a 20k Ω resistor.
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The
13
SRT
reset timeout period can be calculated as follows: Reset Timeout (s) = 2.06 x 10 6 ( Ω ) x C SRT (F). Do
not set the reset timeout period to more than 1.12s. For the internal timeout period of 140ms (min),
connect SRT to V CC .
Active-Low Reset Output. RESET asserts low when the voltage on any of the UVIN_ inputs falls below
their respective thresholds, the voltage on any of the OVIN_ inputs goes above its respective
19
RESET
threshold, or MR is asserted. RESET remains asserted for at least the minimum reset timeout after all
monitored UVIN_ inputs exceed their respective thresholds, all OVIN_ inputs fall below their
respective thresholds, and MR is deasserted. This open-drain output has a 30μA internal pullup.
Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low
EP
thermal resistance path from the IC junction to the PC board. Do not use as the only electrical
connection to GND.
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