参数资料
型号: MAX16062ETG+T
厂商: Maxim Integrated Products
文件页数: 17/18页
文件大小: 0K
描述: IC SUPERVISOR OCT 1% 24TQFN-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 多压监控器
监视电压数目: 8
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 140 ms/可调最小值
电压 - 阀值: 8 种可选阀值组合
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-WFQFN 裸露焊盘
供应商设备封装: 24-TQFN-EP(4x4)
包装: 带卷 (TR)
1% Accurate, Quad-/Hex-/Octal-Voltage
μP Supervisors
Margin Output Disable ( MARGIN )
MARGIN allows system-level testing while power sup-
plies are adjusted from their nominal voltages. Drive
MARGIN low to force RESET and OUT_ high, regard-
less of the voltage at any monitored input. The state of
each output does not change while MARGIN = GND.
The watchdog timer continues to run when
MARGIN is low, and if a timeout occurs, RESET will
assert t MD after MARGIN is deasserted.
The MARGIN input is internally pulled up to V CC . Leave
MARGIN unconnected or connect to V CC if unused.
Undervoltage Lockout (UVLO)
The MAX16060/MAX16061/MAX16062 feature a V CC
undervoltage lockout (UVLO) that preserves a reset
status even if V CC falls as low as 1V. The undervoltage
lockout circuitry monitors the voltage at V CC . If V CC
falls below the UVLO falling threshold (typically
1.735V), RESET is asserted and all OUT_ are asserted
low. This eliminates an incorrect RESET or OUT_ output
state as V CC drops below the normal V CC operational
voltage range of 1.98V to 5.5V.
During power-up as V CC rises above 1V, RESET is
asserted and all OUT_ are asserted low until V CC
exceeds the UVLO threshold. As V CC exceeds the UVLO
threshold, all inputs are monitored and the correct output
state appears at all the outputs. This also ensures that
RESET and all OUT_ are in the correct state once V CC
reaches the normal V CC operational range.
Power-Supply Bypassing
In noisy applications, bypass V CC to ground with a
0.1μF capacitor as close to the device as possible. The
additional capacitor improves transient immunity. For
fast-rising V CC transients, additional capacitance may
be required.
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