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参数资料
| 型号： | MAX16062ETG+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/18页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR OCT 1% 24TQFN-EP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 多压监控器 |
| 监视电压数目： | 8 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 140 ms/可调最小值 |
| 电压 - 阀值： | 8 种可选阀值组合 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 供应商设备封装： | 24-TQFN-EP（4x4） |
| 包装： | 带卷 (TR) |
1% Accurate, Quad-/Hex-/Octal-Voltage
μP Supervisors
Pin Description (MAX16062)
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
—
NAME
IN5
IN6
IN7
IN8
WDI
GND
V CC
OUT5
OUT6
OUT7
OUT8
MR
SRT
MARGIN
OUT4
OUT3
OUT2
OUT1
RESET
IN1
IN2
IN3
IN4
TOL
EP
FUNCTION
Monitored Input Voltage 5. See Table 1 for the input voltage threshold.
Monitored Input Voltage 6. See Table 1 for the input voltage threshold.
Monitored Input Voltage 7. See Table 1 for the input voltage threshold.
Monitored Input Voltage 8. See Table 1 for the input voltage threshold.
Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period, RESET is
asserted and the timer is cleared. The timer also clears whenever a reset is asserted or a rising or falling edge on
WDI is detected. The watchdog timer enters a startup period that allows 54s for the first transition to occur before
a reset. Leave WDI unconnected to disable the watchdog timer. The WDI unconnected state detector uses a
small 400nA current. Therefore, do not connect WDI to anything that will source or sink more than 200nA. Note
that the leakage current specification for most three-state drivers exceeds 200nA.
Ground
Unmonitored Power-Supply Input
Output 5. When the voltage at IN5 falls below its threshold, OUT5 goes low and stays low until the voltage at IN5
exceeds its threshold. The open-drain output has a 30μA internal pullup to V CC .
Output 6. When the voltage at IN6 falls below its threshold, OUT6 goes low and stays low until the voltage at IN6
exceeds its threshold. The open-drain output has a 30μA internal pullup to V CC .
Output 7. When the voltage at IN7 falls below its threshold, OUT7 goes low and stays low until the voltage at IN7
exceeds its threshold. The open-drain output has a 30μA internal pullup to V CC .
Output 8. When the voltage at IN8 falls below its threshold, OUT8 goes low and stays low until the voltage at IN8
exceeds its threshold. The open-drain output has a 30μA internal pullup to V CC .
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset timeout period
after MR is deasserted. MR is pulled up to V CC through a 20k Ω resistor.
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The reset timeout
period can be calculated as follows:
Reset Timeout (s) = 2.06 x 10 6 ( Ω ) x C SRT (F). For the internal timeout period of 140ms (min), connect SRT to V CC .
Margin Disable Input. Pull MARGIN low to deassert all outputs (go into high state), regardless of the voltage at
any monitored input.
Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the voltage at IN4
exceeds its threshold. The open-drain output has a 30μA internal pullup to V CC .
Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the voltage at IN3
exceeds its threshold. The open-drain output has a 30μA internal pullup to V CC .
Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the voltage at IN2
exceeds its threshold. The open-drain output has a 30μA internal pullup to V CC .
Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the voltage at IN1
exceeds its threshold. The open-drain output has a 30μA internal pullup to V CC .
Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its respective
threshold or MR is asserted. RESET remains asserted for the reset timeout period after all monitored voltages
exceed their respective thresholds and MR is deasserted. This open-drain output has a 30μA internal pullup.
Monitored Input Voltage 1. See Table 1 for the input voltage threshold.
Monitored Input Voltage 2. See Table 1 for the input voltage threshold.
Monitored Input Voltage 3. See Table 1 for the input voltage threshold.
Monitored Input Voltage 4. See Table 1 for the input voltage threshold.
Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to V CC to select
10% threshold tolerance.
Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low thermal resistance
path from the IC junction to the PCB. Do not use as the electrical connection to GND.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
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| MAX16063TG+ | 功能描述:监控电路 Quad Window Voltage Detector RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| MAX16063TG+T | 功能描述:监控电路 Quad Window Voltage Detector RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| MAX16064ETX+ | 功能描述:监控电路 Power-Supply Controller RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
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