参数资料
型号: MAX16071ETL+T
厂商: Maxim Integrated Products
文件页数: 13/52页
文件大小: 0K
描述: IC SYSTEM MANAGER 8CH 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 电源监控器
电源电压: 2.8 V ~ 14 V
电流 - 电源: 4.5mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 带卷 (TR)
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Boot-Up Delay
Once EN is above its threshold and the software-enable
bit is set, a boot-up delay occurs before monitoring
begins. This delay is configured in register r77h[3:0] as
shown in Tables 2 and 3.
Internal Current-Sense Amplifier
The current-sense inputs, CSP/CSM, and a current-
sense amplifier facilitate power monitoring (see Figure
4). The voltage on CSP relative to GND is also monitored
by the ADC when the current-sense amplifier is enabled
with r47h[0]. The conversion results are located in regis-
ters r19h and r1Ah (see Table 6). There are two select-
able voltage ranges for CSP set by r47h[1], see Table
4. Although the voltage can be monitored over SMBus
or JTAG, this voltage has no threshold comparators and
cannot trigger any faults. Regarding the current-sense
amplifier, there are four selectable ranges and the ADC
output for a current-sense conversion is:
X ADC = (V SENSE x A V )/1.4V x (2 8 - 1)
where X ADC is the 8-bit decimal ADC result in register
r18h, V SENSE is V CSP - V CSM, and A V is the current-
sense voltage gain set by r47h[3:2].
Table 2. Boot-Up Delay Register
In addition, there are two programmable current-sense
trip thresholds: primary overcurrent and secondary over-
current. For fast fault detection, the primary overcurrent
threshold is implemented with an analog comparator
connected to the internal OVERC signal. The OVERC
signal can be output on one of the GPIO_s. See the
General-Purpose Inputs/Outputs section for configur-
ing the GPIO_ to output the OVERC signal. The primary
threshold is set by:
I TH = V CSTH /R SENSE
where I TH is the current threshold to be set, V CSTH is
the threshold set by r47h[3:2], and R SENSE is the value
of the sense resistor. See Table 4 for a description of
r47h. OVERC depends only on the primary overcurrent
threshold. The secondary overcurrent threshold is imple-
mented through ADC conversions and digital compari-
son set by r6Ch. The secondary overcurrent threshold
includes programmable time delay options located in
r73h[6:5]. Primary and secondary current-sense faults
are enabled/disabled through r47h[0].
REGISTER
ADDRESS
77h
FLASH
ADDRESS
277h
BIT RANGE
[3:0]
[7:0]
Boot-up delay
Reserved
DESCRIPTION
Table 3. Boot-Up Delay Values
CODE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
VALUE
25 F s
500 F s
1ms
2ms
3ms
4ms
6ms
8ms
10ms
12ms
25ms
100ms
200ms
400ms
800ms
1.6s
______________________________________________________________________________________
13
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