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参数资料
| 型号： | MAX16071ETL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 35/52页 |
| 文件大小： | 0K |
| 描述： | IC SYSTEM MANAGER 8CH 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 电源监控器 |
| 电源电压： | 2.8 V ~ 14 V |
| 电流 - 电源： | 4.5mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
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12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Receive Byte
7)
The slave asserts an ACK on the data line.
The receive byte protocol allows the master device to
read the register content of the MAX16070/MAX16071
(see Figure 11). The flash or register address must be
preset with a send byte or write word protocol first. Once
the read is complete, the internal pointer increases by
one. Repeating the receive byte protocol reads the con-
tents of the next address. The receive byte procedure
follows:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a read
bit (high).
8) The master sends an 8-bit PEC byte.
9) The slave asserts an ACK on the data line (if PEC is
good, otherwise NACK).
10) The master generates a STOP condition.
Read Byte
The read byte protocol (see Figure 11) allows the master
device to read a single byte located in the default page,
extended page, or flash page depending on which page
is currently selected. The read byte procedure is the
following:
3) The addressed slave asserts an ACK on SDA.
4) The slave sends 8 data bits.
5 The master asserts a NACK on SDA.
6) The master generates a STOP condition.
Write Byte
The write byte protocol (see Figure 11) allows the master
device to write a single byte in the default page, extend-
ed page, or flash page, depending on which page is cur-
rently selected. The write byte procedure is the following:
1) The master sends a START condition.
1)
2)
3)
4)
5)
6)
7)
8)
The master sends a START condition.
The master sends the 7-bit slave address and a
write bit (low).
The addressed slave asserts an ACK on SDA.
The master sends an 8-bit memory address.
The addressed slave asserts an ACK on SDA.
The master sends a REPEATED START condition.
The master sends the 7-bit slave address and a
read bit (high).
The addressed slave asserts an ACK on SDA.
2) The master sends the 7-bit slave address and a write
bit (low).
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit memory address.
5) The addressed slave asserts an ACK on SDA.
6) The master sends an 8-bit data byte.
9) The slave sends an 8-bit data byte.
10) The master asserts a NACK on SDA.
11) The master sends a STOP condition.
If the memory address is not valid, it is NACKed by the
slave at step 5 and the address pointer is not modified.
When PEC is enabled, the Read Byte protocol becomes:
7) The addressed slave asserts an ACK on SDA.
8) The master sends a STOP condition.
To write a single byte, only the 8-bit memory address
and a single 8-bit data byte are sent. The data byte is
written to the addressed location if the memory address
is valid. The slave asserts a NACK at step 5 if the mem-
ory address is not valid.
When PEC is enabled, the Write Byte protocol becomes:
1)
2)
3)
4)
5)
6)
The master sends a START condition.
The master sends the 7-bit slave ID plus a write
bit (low).
The addressed slave asserts an ACK on the data line.
The master sends 8-bit memory address.
The active slave asserts an ACK on the data line.
The master sends a REPEATED START condition.
1)
2)
The master sends a START condition.
The master sends the 7-bit slave ID plus a write
bit (low).
7)
8)
9)
The master sends the 7-bit slave ID plus a read bit (high).
The addressed slave asserts an ACK on the data line.
The slave sends 8 data bits.
3)
4)
5)
6)
The addressed slave asserts an ACK on the data line.
The master sends an 8-bit memory address.
The active slave asserts an ACK on the data line.
The master sends an 8-bit data byte.
10) The master asserts an ACK on the data line.
11) The slave sends an 8-bit PEC byte.
12) The master asserts a NACK on the data line.
13) The master generates a STOP condition.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX16072RS15D0+T | 功能描述:监控电路 uP Supervisor 1.58V Trip RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| MAX16072RS15D1+T | 功能描述:监控电路 uP Supervisor 1.58V Trip RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| MAX16072RS15D2+T | 功能描述:监控电路 uP Supervisor 1.58V Trip RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| MAX16072RS15D3+T | 功能描述:监控电路 uP Supervisor 1.58V Trip RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| MAX16072RS16D0+T | 功能描述:监控电路 uP Supervisor 1.63V Trip RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
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