参数资料
型号: MAX16809ATU+T
厂商: Maxim Integrated
文件页数: 17/20页
文件大小: 0K
描述: IC LED DRVR WT/RGB BCKLT 38-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
恒定电流:
拓扑: 开路漏极,PWM,降压(降压),SEPIC,升压(升压)
输出数: 16
内部驱动器:
类型 - 主要: 背光
类型 - 次要: RGB,白色 LED
频率: 20kHz ~ 1MHz
电源电压: 8 V ~ 26.5 V
输出电压: 36V
安装类型: 表面贴装
封装/外壳: 38-WFQFN 裸露焊盘
供应商设备封装: 38-TQFN(5x7)
包装: 带卷 (TR)
工作温度: -40°C ~ 125°C
Integrated 16-Channel LED Driver with
Switch-Mode Boost and SEPIC Controller
Stand-Alone Operation
In stand-alone operation, the MAX16809 does not use
the 4-wire interface (see the Typical Operating
Circuits). Connect DIN and LE to V+ and provide at
least 16 external clock pulses to CLK to enable 16 out-
put ports. This startup pulse sequence can be provided
either using an external clock or the PWM signal. The
external clock can also be generated using the signal
at RTCT and an external comparator.
LED Dimming
PWM Dimming
All the output channels can be dimmed simultaneously
by applying a PWM signal (50Hz to 30kHz) to OE . This
allows for a wide range of dimming up to a 5000:1 ratio.
Each channel can be independently turned on and off
using a 4-wire serial interface. The dimming is propor-
tional to the PWM duty cycle.
LED Current Amplitude Adjustment
Using an analog or digital potentiometer as R SET allows
for LED current amplitude adjustment and linear dimming.
Computing Power Dissipation
Use the following equation to estimate the upper limit
power dissipation (PD) for the MAX16809:
? i = 15 ?
PD = DUTY × ? ( V + x I + ) + ∑ V OUTi x I OUTi ?
? ?
? i = 0 ?
+ ( V CC xI CC )
where:
V+ = supply voltage
I+ = V+ operating supply current
DUTY = PWM duty cycle applied to OE
V OUTi = MAX16809 port output voltage when driving
load LED(s)
I OUTi = LED drive current programmed by R SET
PD = power dissipation
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. Use a multilayer
board whenever possible for better noise immunity.
Protect sensitive analog grounds by using a star
ground configuration. Minimize ground noise by con-
necting AGND, PGND, the input bypass-capacitor
ground lead, and the output-filter ground lead to a sin-
gle point (star ground configuration). Also, minimize
trace lengths to reduce stray capacitance, trace resis-
tance, and radiated noise. The trace between the out-
put voltage-divider and the FB pin must be kept short,
as well as the trace between AGND and PGND.
______________________________________________________________________________________
17
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