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参数资料
| 型号： | MAX16825AUE+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 3/13页 |
| 文件大小： | 0K |
| 描述： | IC LED DRVR HIGH BRIGHT 16-TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 恒定电流： | 是 |
| 拓扑： | 线性，开路漏极，PWM |
| 输出数： | 3 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 车载，背光 |
| 类型 - 次要： | 高亮度 LED（HBLED） |
| 电源电压： | 6.5 V ~ 28 V |
| 输出电压： | 36V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 16-TSSOP-EP |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 125°C |
MAX16824/MAX16825
High-Voltage, Three-Channel Linear
High-Brightness LED Drivers
ELECTRICAL CHARACTERISTICS (continued)
(V IN = 12V, C REG = 1μF to GND, I REG = 0, R CS_ = 2 ? from CS_ to GND, T J = T A = -40°C to +125°C, unless otherwise noted. Typical
values are at T J = T A = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUTS (OUT1, OUT2, OUT3)
Turn-On Time
Turn-Off Time
t R
t F
PWM_ rising time, t R , is measured from 20%
to 80% of I OUT_
PWM_ falling time, t F , is measured from
80% to 20% of I OUT_
1
1
μs
μs
SPI INTERFACE (CLK, LE, OE , DIN, DOUT) (Figures 3 and 4)
DIN, CLK, LE, OE Input Bias
Current
DIN, CLK, LE, OE Input-Voltage
High
DIN, CLK, LE, OE Input-Voltage
Low
V IH
V IL
V DIN = V CLK = V LE = V OE = 0 or 5V
2.2
1
0.5
μA
V
V
CLK Clock Period
CLK Pulse-Width High
CLK Pulse-Width Low
DIN Setup Time
DIN Hold Time
DOUT Propagation Delay
DOUT Rise/Fall Time
DOUT Voltage High
DOUT Voltage Low
LE Pulse-Width High
LE Setup Time
LE Rising to OUT_ Rising Delay
LE Rising to OUT_ Falling Delay
t CP
t CH
t CL
t DS
t DH
t DO
t DR /t DF
V DOH
V DOL
t LW
t LS
t LRR
t LRF
50% of CLK rising to 50% of next CLK
rising, Figure 3
50% of CLK rising to 50% of CLK falling,
Figure 3
50% of CLK falling to 50% of CLK rising,
Figure 3
50% of DIN rising to 50% of CLK rising,
Figure 3
50% of CLK rising to 50% of DIN falling,
Figure 3
50% of CLK rising to 50% of DOUT rising/
falling, Figure 3
C DOUT = 10pF, 10% to 90% of DOUT
rising/falling edge (Note 7)
I SOURCE = 4mA
I SINK = 4mA
50% of LE rising to 50% of LE falling,
Figure 3
50% of CLK rising to 50% of LE rising,
Figure 3
50% of LE rising to 50% of OUT_ rising,
Figure 4
50% of LE rising to 50% of OUT_ falling,
Figure 4
50
24
24
5
10
5
4.5
20
15
15
0.5
150
475
ns
ns
ns
ns
ns
ns
ns
V
V
ns
ns
ns
ns
Maxim Integrated
3
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