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参数资料
| 型号： | MAX16825AUE+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 6/13页 |
| 文件大小： | 0K |
| 描述： | IC LED DRVR HIGH BRIGHT 16-TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 恒定电流： | 是 |
| 拓扑： | 线性，开路漏极，PWM |
| 输出数： | 3 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 车载，背光 |
| 类型 - 次要： | 高亮度 LED（HBLED） |
| 电源电压： | 6.5 V ~ 28 V |
| 输出电压： | 36V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 16-TSSOP-EP |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 125°C |
MAX16824/MAX16825
High-Voltage, Three-Channel Linear
High-Brightness LED Drivers
Pin Description
PIN
MAX16824
1
2
3
4
5, 6, 10, 14
7
8
9
11
12
13
15
16
—
MAX16825
1
2
3
4
5, 14
—
—
—
11
12
13
15
16
7
NAME
OUT1
CS1
IN
REG
N.C.
PWM1
PWM2
PWM3
GND
OUT3
CS3
CS2
OUT2
DIN
FUNCTION
Channel 1 LED Driver Output. OUT1 is an open-drain, constant-current-sinking output
rated to 36V.
Channel 1 Sense Amplifier Negative Input. Connect a current-sense resistor between
CS1 and GND to program the output current level for channel 1.
Positive Input Supply. Bypass with a 0.1μF (min) capacitor to GND.
+5V-Regulated Output. Connect a 1μF capacitor from REG to GND.
No Connection. Must be left unconnected.
Dimming Input 1. PWM1 is a dimming input for channel 1. A logic-low turns off OUT1 and
a logic-high turns on OUT1.
Dimming Input 2. PWM2 is a dimming input for channel 2. A logic-low turns off OUT2 and
a logic-high turns on OUT2.
Dimming Input 3. PWM3 is a dimming input for channel 3. A logic-low turns off OUT3 and
a logic-high turns on OUT3.
Ground
Channel 3 LED Driver Output. OUT3 is an open-drain, constant-current-sinking output
rated to 36V.
Channel 3 Sense Amplifier Negative Input. Connect a current-sense resistor between
CS3 and GND to program the output current level for channel 3.
Channel 2 Sense Amplifier Negative Input. Connect a current-sense resistor between
CS2 and GND to program the output current level for channel 2.
Channel 2 LED Driver Output. OUT2 is an open-drain, constant-current-sinking output
rated to 36V.
Serial-Data Input. Data is loaded into the internal 3-bit shift register on the rising edge of
CLK.
Latch-Enable Input. Data loaded transparently from the internal shift register to the
—
8
LE
output latch while LE is high. Data is latched into the output latch on the LE’s falling edge
and retained while LE is low.
Output Enable Input. Drive OE high to place all outputs into a high-impedance mode
—
9
OE
without altering the contents of the output latches. Drive OE low to force all outputs to
follow the state of the output latches.
6
—
—
—
10
6
—
DOUT
CLK
EP
Serial-Data Output. Data is clocked out of the internal 3-bit shift register to DOUT on the
rising edge of CLK. DOUT is a replica of the shift register’s last bit.
Clock Input
Exposed Pad. Connect EP to a large-area ground plane for effective power dissipation.
Do not use as the IC ground connection.
Maxim Integrated
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