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参数资料
| 型号： | MAX1685EEE-T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 4/14页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC 3.3V/ADJ 16QSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 两者兼有 |
| 输出数： | 1 |
| 输出电压： | 3.3V，1.25 V ~ 14 V |
| 输入电压： | 2.7 V ~ 14 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 600kHz |
| 电流 - 输出： | 1A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-QSOP |
Low-Noise, 14V Input, 1A, PWM
Step-Down Converters
ELECTRICAL CHARACTERISTICS
(V IN = V SHDN = 6V, STBY = SYNC/PWM = CVL, V BOOT = V OUT , FB = AGND, circuit of Figure 1, T A = -40°C to +85°C , unless other-
wise noted.) (Note 5)
PARAMETER
Input Voltage Range
Output Feedback Voltage
Output Voltage (3.3V Mode)
Output Current Capability
Output Adjust Range
FB Input Current
Current Limit in PWM Mode
Current Limit in Low-Power
Mode
Quiescent Power Consumption
Shutdown Supply Current
Oscillator Frequency
Reference Output Voltage
CVL Regulator Output Voltage
CVL Undervoltage Lockout
Threshold
CVH with Respect to V IN
BOOT Switchover Threshold
ILIM/SS Source Current
Logic Input High Voltage
Logic Input Low Voltage
SYMBOL
V FB
V OUT
I FB
I LIM
I LIMLP
f OSC
V IH
V IL
CONDITIONS
V FB = V OUT , I LOAD = 0 to 1A
FB = AGND, I LOAD = 0 to 1A
V IN = 6V to 14V
BOOT = AGND (Note 1)
V FB = 1.4V
STBY = low
Normal mode, SYNC/PWM = low,
V BOOT = 3.3V (Note 2)
Low-power mode, STBY = low,
V BOOT = 3.3V (Note 2)
SHDN = low
MAX1684
MAX1685
I REF = 0
V IN = 3V to 14V, BOOT = AGND,
I CVL = 0 to 5mA
BOOT = AGND, CVL falling edge,
typical hysteresis is 40mV
I CVH = -1mA
BOOT falling edge, typical hysteresis is 0.1V
V ILIM/SS = 1.4V
SHDN , STBY , SYNC/PWM
MIN
2.7
1.233
3.280
1
V REF
-50
1.2
285
240
480
1.232
2.7
2.4
-5.0
2.35
3.1
2
MAX
14
1.269
3.382
V IN
50
2.3
475
2
0.27
6
350
700
1.268
3.15
2.6
-4.1
2.65
4.7
0.7
UNITS
V
V
V
A
V
nA
A
mA
mW
μA
kHz
V
V
V
V
V
μA
V
Note 1: The output adjust range with BOOT connected to V OUT is V REF to 5.5V. Connect BOOT to AGND for V OUT > 5.5V.
Note 2: The quiescent power-consumption specifications include chip supply and gate-drive loss only. Divide these values by V IN
(6V) to obtain quiescent currents. In normal and low-power modes, chip supply current dominates and quiescent power is
proportional to V BOOT (BOOT connected to OUT). In PWM mode, gate-drive loss dominates and quiescent power is propor-
tional to V IN ? (V IN - V CVH ). In addition, IR losses in power switches and external components typically increase PWM quies-
cent power consumption by 5mW to 10mW. Note that if the device is not bootstrapped, additional power is dissipated in the
CVL linear regulator.
Note 3: When the duty factor (V OUT / V IN ) is less than this value, the switching frequency decreases in PWM mode to maintain
regulation.
Note 4: Thermal shutdown is disabled in low-power mode ( STBY = low) to reduce power consumption.
Note 5: Specifications to -40°C are guaranteed by design, not production tested.
4
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