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参数资料
| 型号： | MAX16977SAUE/V+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 14/18页 |
| 文件大小： | 0K |
| 描述： | IC BUCK SYNC ADJ 2A 16TSSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 两者兼有 |
| 输出数： | 1 |
| 输出电压： | 5V，1 V ~ 10 V |
| 输入电压： | 3.5 V ~ 36 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1MHz ~ 2.2MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 包装： | * |
| 供应商设备封装： | * |
MAX16977
36V, 2A, 2.2MHz Step-Down Converter
with Low Operating Current
The output capacitance must be high enough to absorb
the inductor energy while transitioning from full-load
to no-load conditions without tripping the overvoltage
fault protection. When using high-capacitance, low-ESR
capacitors, the filter capacitor’s ESR dominates the
output-voltage ripple. So the size of the output capaci-
tor depends on the maximum ESR required to meet the
output-voltage ripple (V RIPPLE(P-P) ) specifications:
V RIPPLE(P-P) = ESR × I LOAD(MAX) × LIR
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as
to the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value.
When using low-capacity filter capacitors, such as
ceramic capacitors, size is usually determined by the
capacity needed to prevent voltage droop and volt-
age rise from causing problems during load transients.
Generally, once enough capacitance is added to meet
the overshoot requirement, undershoot at the rising load
edge is no longer a problem. However, low-capacity filter
capacitors typically have high-ESR zeros that can affect
the overall stability.
Rectifier Selection
The device requires an external Schottky diode recti-
fier as a freewheeling diode. Connect this rectifier close
to the device using short leads and short PCB traces.
Choose a rectifier with a voltage rating greater than the
maximum expected input voltage, V SUPSW . Use a low
forward-voltage-drop Schottky rectifier to limit the nega-
tive voltage at LX. Avoid higher than necessary reverse-
voltage Schottky rectifiers that have higher forward-
voltage drops.
V OUT
Compensation Network
The device uses an internal transconductance error
amplifier with its inverting input and its output available
to the user for external frequency compensation. The
output capacitor and compensation network determine
the loop stability. The inductor and the output capaci-
tor are chosen based on performance, size, and cost.
Additionally, the compensation network optimizes the
control-loop stability.
The controller uses a current-mode control scheme that
regulates the output voltage by forcing the required current
through the external inductor. The device uses the volt-
age drop across the high-side MOSFET to sense inductor
current. Current-mode control eliminates the double pole
in the feedback loop caused by the inductor and output
capacitor, resulting in a smaller phase shift and requiring
less elaborate error-amplifier compensation than voltage-
mode control. Only a simple single-series resistor (R C )
and capacitor (C C ) are required to have a stable, high-
bandwidth loop in applications where ceramic capacitors
are used for output filtering ( Figure 3 ). For other types of
capacitors, due to the higher capacitance and ESR, the
frequency of the zero created by the capacitance and
ESR is lower than the desired closed-loop crossover fre-
quency. To stabilize a nonceramic output capacitor loop,
add another compensation capacitor (C F ) from COMP to
GND to cancel this ESR zero.
The basic regulator loop is modeled as a power modula-
tor, output feedback divider, and an error amplifier. The
power modulator has a DC gain set by g mc x R LOAD ,
with a pole and zero pair set by R LOAD , the output
capacitor (C OUT ), and its ESR. The following equations
allow to approximate the value for the gain of the power
modulator (GAIN MOD(DC) ), neglecting the effect of the
ramp stabilization. Ramp stabilization is necessary when
the duty cycle is above 50% and is internally done for
the device.
R1
=
GAIN MOD(DC) g mc × R LOAD
R2
V REF
g m
R C
COMP
C F
where R LOAD = V OUT /I LOUT(MAX) in I and g mc = 3S.
C C
Figure 3. Compensation Network
Maxim Integrated
14
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