参数资料
型号: MAX17000EVKIT+
厂商: Maxim Integrated Products
文件页数: 13/32页
文件大小: 0K
描述: KIT EVAL FOR MAX17000
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: 特殊用途 DC/DC,DDR 存储器电源
输出及类型: 3,非隔离
功率 - 输出: 19.8W
输出电压: 1.8V,0.9V,0.9V
电流 - 输出: 10A,2A,3mA
输入电压: 7 ~ 20 V
稳压器拓扑结构: 降压
频率 - 开关: 300kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: MAX17000
MAX17000
Complete DDR2 and DDR3 Memory
Power-Management Solution
Pin Description (continued)
PIN
14
15
16
17
18
19
20
21
22
23
NAME
TON
DH
LX
BST
DL
V DD
PGND1
AGND
SKIP
V CC
FUNCTION
Switching Frequency Setting Input. An external resistor between the input power source and this
pin sets the switching frequency per phase according to the following equation:
T SW = C TON x (R TON + 6.5k )
where C TON = 16.26pF.
TON is high impedance in shutdown.
High-Side Gate-Driver Output. Swings from LX to BST. DH is low when in shutdown or UVLO.
Inductor Connection. Connect LX to the switched side of the inductor as shown in Figure 1.
Boost Flying Capacitor Connection. Connect to an external 0.1μF, 6V capacitor as shown in Figure
1. The MAX17000 contains an internal boost switch.
Synchronous-Rectifier Gate-Driver Output. DL swings from V DD to PGND1.
Supply Voltage Input for the DL Gate Driver and 3.3V Reference/Analog Supply. Connect to the
system supply voltage (+4.5V to +5.5V). Bypass V DD to power ground with a 1 μF or greater
ceramic capacitor.
Power Ground. Ground connection for the low-side MOSFET gate driver.
Analog Ground. Connect backside exposed pad to AGND.
Pulse-skipping Control Input. This input determines the mode of operation under normal steady-
state conditions and dynamic output voltage transitions:
High (> 2.4V) = Forced-PWM operation
Low (AGND) = Pulse-skipping mode
Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass V CC to AGND with a 1μF or
greater ceramic capacitor.
Shutdown Control Input. Connect to V CC for normal operation. When SHDN is pulled low, the
MAX17000 slowly ramps down the output voltage to ground. When the internal target voltage
reaches 25mV, the controller forces DL low, and enters the low current (1μA) shutdown state.
24
SHDN
When discharge mode is enabled by OVP (OVP = high), the CSL and VTT internal 16
discharge
MOSFETs are enabled in shutdown. When discharge mode is disabled by OVP (OVP = low), LX,
VTT, and VTTR are high impedance in shutdown.
A rising edge on SHDN clears the fault OV protection latch.
Maxim Integrated
EP
Exposed Pad. Connect backside exposed pad to AGND.
13
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