参数资料
型号: MAX17010ETL+T
厂商: Maxim Integrated Products
文件页数: 12/17页
文件大小: 0K
描述: IC LCD DISPLAY BIAS 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: LCD 监视器,笔记本电脑显示器
电流 - 电源: 50µA
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 带卷 (TR)
Internal-Switch Boost Regulator with Integrated
High-Voltage Level Shifter and Op Amp
D ≈ MAIN IN
The regulator controls the output voltage, and the power
delivered to the output, by modulating the duty cycle (D)
of the internal power MOSFET in each switching cycle.
The duty cycle of the MOSFET is approximated by:
V ? V
V MAIN
Figure 3 shows the block diagram of the step-up regu-
lator. An error amplifier compares the signal at FB to
1.235V and changes the COMP output. The voltage at
COMP determines the current trip point each time the
internal MOSFET turns on. As the load varies, the error
amplifier sources or sinks current to the COMP output
accordingly, to produce the inductor peak current ne-
cessary to service the load. To maintain stability at high
duty cycles, a slope-compensation signal is summed
with the current-sense signal.
On the rising edge of the internal clock, the controller
sets a flip-flop, turning on the n-channel MOSFET, and
applying the input voltage across the inductor. The cur-
rent through the inductor ramps up linearly, storing
energy in its magnetic field. Once the sum of the cur-
rent-feedback signal and the slope compensation
CLOCK
exceed the COMP voltage, the controller resets the flip-
flop and turns off the MOSFET. Since the inductor cur-
rent is continuous, a transverse potential develops
across the inductor that turns on the diode (D1). The
voltage across the inductor then becomes the diffe-
rence between the output voltage and the input volt-
age. This discharge condition forces the current
through the inductor to ramp back down, transferring
the energy stored in the magnetic field to the output
capacitor and the load. The MOSFET remains off for the
rest of the clock cycle.
Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) circuit compares the
input voltage at IN with the UVLO threshold (1.3V rising
and 1.2V falling) to ensure that the input voltage is high
enough for reliable operation. The 100mV (typ) hysteresis
prevents supply transients from causing a restart. Once
the input voltage exceeds the UVLO rising threshold,
startup begins. When the input voltage falls below the
UVLO falling threshold, the controller turns off the main
step-up regulator and the linear regulator outputs, dis-
ables the switch-control block, and the op amp outputs
are high impedance.
LX
LOGIC AND
DRIVER
PGND
CURRENT-LIMIT
COMPARATOR
+
SLOPE COMP
PWM
-
SOFT-
START
I LIMIT
1.2MHz
OSCILLATOR
COMPARATOR
+
-
CURRENT
SENSE
-
TO FAULT LOGIC
FAULT
+
1.0V
ERROR AMP
+
FB
COMPARATOR
-
1.235V
COMP
Figure 3. Step-Up Regulator Block Diagram
12
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