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| 型号： | MAX17021GTL+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 29/48页 |
| 文件大小： | 0K |
| 描述： | IC CTLR PWM DUAL IMVP-6+ 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 60 |
| 系列： | Quick-PWM™ |
| 应用： | 控制器， Intel IMVP-6+，IMVP-6.5? |
| 输入电压： | 4.5 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 管件 |
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Dual-Phase, Quick-PWM Controllers for
IMVP-6+/IMVP-6.5 CPU Core Power Supplies
Table 3. Operating Mode Truth Table
INPUTS
SHDN
GND
DPRSTP
( SLOW )
X
DPRSLPVR
X
PSI
X
PHASE
OPERATION*
Disabled
OPERATING MODE
Low-Power Shutdown Mode. DL1 and DL2 forced low, and the
controller is disabled. The supply current drops to 1μA (max).
Multiphase
Startup/Boot. When SHDN is pulled high, the MAX17021/
Rising
X
X
X
pulse-skipping
1/8 R TIME slew
MAX17082/MAX17482 begin the startup sequence. The controller
enables the PWM regulator and ramps the output voltage up to the
rate
Multiphase
boot voltage. See Figure 10.
High
X
(High)
Low
High
forced-PWM
nominal R TIME
Full Power. The no-load output voltage is determined by the
selected VID DAC code (D0 –D6, Table 4).
slew rate
1-phase forced-
Intermediate Power. The no-load output voltage is determined by
High
X
(High)
Low
Low
PWM
nominal R TIME
the selected VID DAC code (D0 –D6, Table 4). When PSI is pulled
low, the MAX17021/MAX17082/MAX17482 immediately disable
slew rate
phase 2. DH2 and DL2 are pulled low.
Deeper Sleep Mode. The no-load output voltage is determined
High
Low
(High)
High
X
1-phase pulse-
skipping
nominal R TIME
slew rate
by the selected VID DAC code (D0 –D6, Table 4). When
DPRSLPVR is pulled high, the MAX17021/MAX17082/MAX17482
immediately enter one-phase pulse-skipping operation, allowing
automatic PWM/PFM switchover under light loads. The PWRGD
and CLKEN upper thresholds are blanked during downward
transitions. DH2 and DL2 are pulled low.
Deeper Sleep Slow Exit Mode. The no-load output voltage is
determined by the selected VID DAC code (D0 –D6, Table 4).
When DPRSTP is pulled high while DPRSLPVR is already high,
High
High
(Low)
High
X
1-phase pulse-
skipping
the MAX17021 remains in one-phase pulse-skipping operation,
allowing automatic PWM/PFM switchover under light loads, but
reduces its slew rate to 1/4 of normal. When SLOW is pulled low,
the MAX17082/MAX17482 reduce their slew rate to 1/2 of normal.
The PWRGD and CLKEN upper thresholds are blanked. DH2 and
DL2 are pulled low.
Falling
X
X
X
Multiphase
forced-PWM
1/8 R TIME slew
rate
Shutdown. When SHDN is pulled low, the MAX17021/MAX17082/
MAX17482 immediately pull PWRGD and PHASEGD low, CLKEN
becomes high, all enabled phases are activated, and the output
voltage is ramped down to ground. Once the output reaches 0V,
the controller enters the low-power shutdown state. See Figure 10.
Fault Mode. The fault latch has been set by the MAX17021/
High
X
X
X
Disabled
MAX17082/MAX17482 UVP or thermal-shutdown protection, or by the
OVP protection. The controller remains in fault mode until VCC power
is cycled or SHDN toggled.
*Multiphase operation—all enabled phases active.
______________________________________________________________________________________
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