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参数资料
| 型号： | MAX17080GTL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 33/48页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER AMD SVI 40-TQFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 2.7 V ~ 5.5 V |
| 输出数： | 3 |
| 输出电压： | 0.013 V ~ 1.55 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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AMD 2-/3-Output Mobile Serial
VID Controller
For automatic startup, the battery voltage should be
present before V CC . If the controller attempts to bring
the output into regulation without the battery voltage
present, the fault latch trips. The controller remains shut
down until the fault latch is cleared by toggling SHDN
or cycling the V CC power supply below 0.5V.
If the V CC voltage drops below 4.25V, the controller
assumes that there is not enough supply voltage to
make valid decisions and could also result in the stored
boot VIDs being corrupted. As such, the MAX17080
immediately stops switching (DH_ and DL_ pulled low),
latches off, and discharges the outputs using the inter-
nal 20 ? switches from CSN_ to GND.
Notes for Figure 7:
1) The relationship between DC_IN and V DDIO is not
guaranteed. It is possible to have V DDIO powered
when DC_IN is not powered, and it is possible to
have DC_IN power up before V DDIO powers up.
2) As the V DDIO power rail comes within specification,
VDD_Plane_Strap becomes valid and SVC and SVD
are driven to the boot VID value by the processor.
The system guarantees that V DDIO is in specifica-
tion and SVC and SVD are driven to the boot VID
value for at least 10μs prior to SHDN being asserted
to the MAX17080.
3) After SHDN is asserted, the MAX17080 samples and
latches the VDD_Plane_Strap level at its GNDS1 and
GNDS2 pins when REF reaches the REFOK thresh-
old, and ramps up the voltage plane outputs to the
level indicated by the 2-bit boot VID. The boot VID is
stored in the MAX17080 for use when PGD_IN
deasserts. The MAX17080 soft-starts the output rails
to limit inrush current from the DC_IN rail. The
MAX17080 operates in pulse-skipping mode in the
boot mode regardless of PSI_L settings.
4) The MAX17080 asserts PWRGD. After PWRGD is
asserted and all system-wide voltage planes and
free-running clocks are within specification, then the
system asserts PGD_IN.
5) The processor holds the 2-bit boot VID for at least
10μs after PGD_IN is asserted.
6) The processor issues the set VID command through SVI.
7) The MAX17080 transitions the voltage planes to the
set VID. The set VID can be greater than or less
than the boot VID voltage. The MAX17080 operates
in pulse-skipping mode or forced-PWM mode
according to the PSI_L setting.
8) The chipset enforces a 1ms delay between PGD_IN
assertion and RESET_L deassertion.
PWRGD
The MAX17080 features internal power-good fault com-
parators for each SMPS. The outputs of these individual
power-good fault comparators are logically ORed to drive
the gate of the open-drain PWRGD output transistor.
Each SMPS ’s power-good fault comparator has an
upper threshold of +200mV (typ) and a lower threshold
of -300mV (typ). PWRGD goes low if the output of either
SMPS exceeds its respective threshold.
PWRGD is forced low during the startup sequence up to
20μs after the output is in regulation. The 2-bit boot VID
is stored when PWRGD goes high during the startup
sequence. PWRGD is immediately forced low when
SHDN goes low.
PWRGD is blanked high impedance while any of the
internal SMPS DACs are slewing during a VID transition,
plus an additional 20μs after the DAC transition is com-
pleted. For downward VID transitions, the upper threshold
of the particular power-good fault comparators remains
blanked until the output reaches regulation again.
PWRGD is blanked high impedance for each SMPS
whose internal DAC is in off mode, and is pulled low if
all three SMPS DACs are in off mode.
PWRGD is forced low for a minimum of 20μs when
PGD_IN goes low during normal operation, and
remains low until all SMPS output voltages are within
their respective power-good windows.
PGD_IN
After the SMPS outputs reach the boot voltage, the
MAX17080 switches to the serial-interface mode when
PGD_IN goes high. Anytime during normal operation, a
high-to-low transition on PGD_IN causes the MAX17080
to slew all three internal DACs back to the stored boot
VIDs. PWRGD goes low immediately when PGD_IN goes
low, and stays low until 20μs after the SMPS outputs are
within their respective PWRGD thresholds. The SVC and
SVD inputs are disabled during the time that PGD_IN is
low. The serial interface is reenabled when PGD_IN
goes high again. Figure 8 shows PGD_IN timing.
Shutdown
When SHDN goes low, the MAX17080 enters shutdown
mode. PWRGD is pulled low immediately and forces all
DH and DL low, and all three outputs are discharged
through the 20 ? internal discharge FETs through CSN pin
for core SMPSs and through the OUT3 pin for NB SMPSs.
______________________________________________________________________________________
33
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