参数资料
型号: MAX17080GTL+T
厂商: Maxim Integrated Products
文件页数: 34/48页
文件大小: 0K
描述: IC CONTROLLER AMD SVI 40-TQFN
标准包装: 2,500
应用: 控制器,AMD SVI
输入电压: 2.7 V ~ 5.5 V
输出数: 3
输出电压: 0.013 V ~ 1.55 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 带卷 (TR)
AMD 2-/3-Output Mobile Serial
VID Controller
PSI_L
PULSE-SKIPPING MODE
SVC/SVD
BUS IDLE
2-BIT BOOT VID, SVC/SVD INPUTS DISABLED
BUS IDLE
SMPS V OUT
(HIGH DAC TARGET)
(LOW DAC TARGET)
SMPS V OUT
PGD_IN
TARGET
V OUT
PWRGD
20 μ s
BLANK
HIGH-Z
20 μ s
Figure 8. PGD_IN Timing
R PTC1
V CC
V CC
PLACE R NTC NEXT TO THE
HOTTEST POWER COMPONENT.
R THRM
THRM
MAX17080
PLACE R PTC1 , R PTC2 , AND R PTC3
NEXT TO THE RESPECTIVE SMPS'S
R PTC2
R PTC3
THRM
MAX17080
R NTC
Figure 9. THRM Configuration
GND
POWER COMPONENT.
R THRM
GND
VRHOT Temperature Comparator
The MAX17080 features an independent comparator
with an accurate threshold (V HOT ) that tracks the ana-
log supply voltage (V HOT = 0.3V CC ). Use a resistor-
and thermistor-divider between V CC and GND to gener-
ate a voltage-SMPS overtemperature monitor. Place the
thermistor as close as possible to the MOSFETs and
inductors.
Place three individual thermistors near to each SMPS to
monitor the temperature of the respective SMPS. When
core SMPSs are in combined-mode operation, the cur-
rent-balance circuit balances the currents between
core SMPS phases. As such, the power loss and heat
in each phase should be identical, apart from the
effects of placement and airflow over each phase.
Single thermistors can be placed near either of the
phases and still be effective for core SMPS temperature
monitoring, and one thermistor can be saved. See
Figure 9.
Fault Protection (Latched)
Output Overvoltage Protection (OVP)
The overvoltage protection (OVP) circuit is designed to
protect the CPU against a shorted high-side MOSFET
by drawing high current and blowing the battery fuse.
The MAX17080 continuously monitors the output for an
overvoltage fault. The controller detects an OVP fault if
the output voltage exceeds the set VID DAC voltage by
more than 300mV. The OVP threshold tracks the VID
DAC voltage except during a downward VID transition.
During a downward VID transition, the OVP threshold is
set at 1.85V (typ) until the output reaches regulation,
when the OVP threshold is reset back to 300mV above
the VID setting.
34
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