参数资料
型号: MAX1714BEEE+
厂商: Maxim Integrated Products
文件页数: 8/24页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 16-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 100
PWM 型: 电流模式
输出数: 1
频率 - 最大: 600kHz
占空比: 100%
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
包装: 管件
High-Speed Step-Down Controller
for Notebook Computers
Pin Description
PIN
PIN
NAME
FUNCTION
MAX1714A
MAX1714B
1
2, 9,
11
3
4
1
2
3
DH
N.C.
SHDN
FB
High-Side Gate Driver Output. Swings from LX to BST.
No Connection. These pins are not connected to any internal circuitry. Connect N.C. pins
to the ground plane to enhance thermal conductivity.
Shutdown Control Input. Drive SHDN to AGND to force the MAX1714 into shutdown. Drive
or connect to V CC for normal operation. A rising edge on SHDN clears the fault latch.
Feedback Input. Connect to AGND for a +2.5V fixed output or to V CC for a +3.3V fixed
output, or connect FB to a resistor divider from OUT for an adjustable output.
Output Voltage Connection. Connect directly to the junction of the external and output fil-
5
4
OUT
ter capacitors. OUT senses the output voltage to determine the on-time and also serves
as the feedback input in fixed-output modes.
Current-Limit Threshold Adjustment. Connect ILIM to V CC for 100mV current-limit threshold.
6
5
ILIM
For an adjustable threshold, connect an external voltage source to ILIM, or use a two-resis-
tor divider from REF to AGND. The external adjustment range of 0.5V to 2.0V corresponds to
a current-limit threshold of 50mV to 200mV.
7
8
6
REF
AGND
+2.0V Reference Voltage Output. Bypass to AGND with 0.22μF (minimum) capacitor. Can
supply 50μA for external loads.
Analog Ground.
Power-Good Open-Drain Output. PGOOD is low when the output voltage is more than 6%
10
7
PGOOD
below the normal regulation point or during soft-start. PGOOD is high impedance when
the output is in regulation and the soft-start circuit has terminated.
12
13
14
15
8
9
10
11
GND
PGND
DL
V DD
V CC
Analog and Power Ground. AGND and PGND connect together internally.
Power Ground. Connect directly to the low-side MOSFET’s source. Serves as the negative
input of the current-limit comparator.
Low-Side Gate-Driver Output. Swings from PGND to V DD .
Supply Input for the DL Gate Drive. Connect to the system supply voltage, +4.5V to +5.5V.
Bypass to PGND with a 1μF (min) ceramic capacitor.
Analog-Supply Input. Connect to the system supply voltage, +4.5V to +5.5V, with a series
20 ? resistor. Bypass to AGND with a 1μF (min) ceramic capacitor.
On-Time Selection-Control Input. This is a four-level input used to determine DH on-time.
16
12
TON
Connect to AGND, REF, or V CC , or leave TON unconnected to set the following switching
frequencies: AGND = 600kHz, REF = 450kHz, floating = 300kHz, and V CC = 200kHz.
17
18
19
13
14
15
V+
SKIP
BST
Battery Voltage Sense Connection. Connect to input power source. V+ is used only to set
the PWM one-shot timing.
Pulse-Skipping Control Input. Connect to V CC for low-noise forced-PWM mode. Connect
to AGND to enable pulse-skipping operation.
Boost Flying-Capacitor Connection. Connect to an external capacitor and diode according
to the Standard Application Circuit (Figure 1). See MOSFET Gate Drivers (DH, DL) section.
External Inductor Connection. Connect LX to the switched side of the inductor. LX serves
20
16
LX
as the lower supply rail for the DH high-side gate driver. LX is also the positive input to the
current-limit comparator.
8
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