参数资料
型号: MAX17535ETG+
厂商: Maxim Integrated Products
文件页数: 24/28页
文件大小: 0K
描述: IC SMBUS BATT CHRGR HF 24TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 75
功能: 充电管理
电池化学: 锂离子(锂离子),多化学
电源电压: 8 V ~ 26 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-WFQFN 裸露焊盘
供应商设备封装: 24-TQFN-EP(4x4)
包装: 管件
High-Frequency,
Low-Cost SMBus Chargers
t ON =
I RIPPLE = BATT OFF
f =
+ t OFF
I DIS = × = 367mA
controller to initiate a new cycle. If the peak inductor
current exceeds IMAX comparator threshold or the output
voltage exceeds the OVP threshold, then the on-time is
terminated. The cycle-by-cycle current limit effectively
protects against overcurrent and short-circuit faults.
If, during the off-time, the inductor current goes to zero, the
ZCMP comparator output pulls high, turning off the low-side
MOSFET. Both the high- and low-side MOSFETs are turned
off until another cycle is ready to begin. The MAX17435/
MAX17535 enter into the discontinuous conduction mode
(see the Discontinuous Conduction section).
The on-time is calculated according to the following
equation:
L × I RIPPLE
V CSSN -V BATT
where:
V × t
L
There is a 0.3 F s minimum off-time when the (V DCIN -
V BATT ) differential becomes too small. If V BATT R 0.88
x V DCIN , then the threshold for minimum off-time is
reached and the off-time is fixed at 0.27 F s. The switching
frequency in this mode varies according to the equation:
1
L × I RIPPLE
V CSSN -V BATT
Discontinuous Conduction
The MAX17435/MAX17535 can also operate in
discontinuous conduction mode to ensure that the
inductor current is always positive. The MAX17435/
MAX17535 enter discontinuous conduction mode when
the output of the LVC control point falls below 110mV. For
RS2 = 10m I , this corresponds to 367mA:
1 110mV
2 15 × RS2
Under extremely light loads, the BST capacitor may
become discharged if there is no DLO pulse. After 192μs
(typ), the MAX17435/MAX17535 turn on DLO for 300ns
and 550ns, respectively, to recharge the BST capacitor.
This DLO pulse need not be followed by a DHI pulse.
Compensation
The CCI loop is internally compensated. The CCV and
the CCS share the external compensation capacitor.
The control loop, which is dominant, uses the external
compensation cap and the one that is not used uses an
internal compensation capacitor.
CCV Loop Compensation
The simplified schematic in Figure 6 is sufficient to
describe the operation of the MAX17435/MAX17535
when the voltage loop (CCV) is in control. The required
compensation network is a pole-zero pair formed with
C CC and R CC, which is an internal 1.7k I . The pole is
necessary to roll off the voltage loop’s response at low
frequency; C CC = 330pF is sufficient for most applications.
MOSFET Drivers
The DHI and DLO outputs are optimized for driving
moderate-sized power MOSFETs. The MOSFET drive
capability is the same for both the low-side and high-
sides switches. This is consistent with the variable duty
factor that occurs in the notebook computer environment
where the battery voltage changes over a wide range.
There must be a low-resistance, low-inductance path
from the DLO driver to the MOSFET gate to prevent shoot-
through. Otherwise, the sense circuitry in the MAX17435/
MAX17535 interprets the MOSFET gate as off while there
is still charge left on the gate. Use very short, wide traces
measuring 10 squares to 20 squares or less (1.25mm to
2.5mm wide if the MOSFET is 25mm from the device).
Unlike the DLO output, the DHI output uses a 50ns (typ)
delay time to prevent the low-side MOSFET from turning
on until DHI is fully off. The same considerations should be
used for routing the DHI signal to the high-side MOSFET.
where I DIS is the current level for discontinuous
conduction.
G M(OUT)
BATT
R ESR
R L
In discontinuous mode, a new cycle is not started until
the LVC voltage rises above 150mV. Discontinuous
mode operation can occur during conditioning charge of
overdischarged battery packs, when the charge current
has been reduced sufficiently by the CCS control loop,
or when the charger is in constant-voltage mode with a
nearly full battery pack.
CC
R CC
C CC
R OGMV
g MV
REF
C OUT
Figure 6. CC Loop Diagram
24
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