参数资料
型号: MAX1775EEE-T
厂商: Maxim Integrated Products
文件页数: 13/16页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 16-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 控制器
输出数: 2
频率 - 最大: 1.25MHz
占空比: 100%
电源电压: 2.7 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
包装: 带卷 (TR)
Dual-Output Step-Down
DC-DC Converter for PDA/Palmtop Computers
IN 2.7V TO 28V
C1
6
8
1 μ F
IN
CVH
M1
C6
10 μ F
ON
OFF
1
SHDNM
PDRV
7
R1
21m ?
MAIN
3.3V
ON
OFF
2
SHDNC
NDRV
4
L M
10 μ H
R2
2A
C4
47 μ F
PGND
GND
INC
C5
C2
1 μ F
C3
0.22 μ F
5 CVL
9
REF
3
14
MAX1775
11
CS+
12
CS-
15
10
FBM
LXC 16
M2
L C
5.4 μ H
R4
CORE
1.8V
22 μ F 1.5A
R3
FBC
13
R5
Figure 4. High Input Voltage Cascaded Configuration
R 1 =
(
)
Design Procedure
Low-Voltage Configuration
To improve efficiency and conserve board space, the
core regulator operates from low input voltages, taking
advantage of internal low-voltage, low-on-resistance
MOSFETs. When the input voltage remains below 5.5V,
run the core converter directly from the input by con-
necting INC to IN (Figure 1). This configuration takes
advantage of the core ’s low-voltage design and
improves efficiency.
High-Voltage Configuration
For input voltages greater than 5.5V, cascade the main
and core converters by connecting INC to the main out-
put voltage. In this configuration (Figure 4), the core
converter is powered from the main output. Ensure that
the main output can simultaneously supply its load and
the core input current. In this configuration, the main
output voltage must be set above the 2.6V minimum
input voltage of the core converter.
Setting the Output Voltages
The main output voltage may be set from +1.25V and
+5.5V with two external resistors connected as a volt-
age-divider to FBM (Figure 1). Resistor values can be
calculated by the following equation:
R2 = R3   [(V OUTM / V FBM ) - 1]
where V FBM = +1.25V. Choose R3 to be 40k ? or less.
The core regulator output is adjustable from +1.0V to
+5.0V through two external resistors connected as a
voltage-divider to FBC (Figure 1). Resistor values can
be calculated through the following equation:
R4 = R5   [(V OUTC / V FBC ) - 1]
where V FBC = +1.0V. Choose R5 to be 30k ? or less.
Setting the Current Limit
The main regulator current limit is set externally through
a small current-sense resistor, R1 (Figure 1). The value
of R1 can be calculated by the following equation:
V CLM
1 . 3 I OUT
where V CLM = 80mV is the current-sense threshold,
and I OUT is the current delivered to the output. The
core converter current limit is set internally and cannot
be modified.
______________________________________________________________________________________
13
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